Moore's law was the exponential improvement path for semiconductors that fueled the computer revolution and enormous worldwide growth. It's a hard act to follow, but there are three new followon trends that seem just as interesting.

Due to high leakage current, Dennard scaling has reached its limit on conventional semiconductor technology. Energy reduction at the transistor level by simply lowering supply voltage has proven to be infeasible for these devices. Some recently proposed millivolt switch techniques aim to mitigate these issues. However, Vdd reduction is constrained by high intermittent error probabilities in millivolt switches. Energy-efficient microarchitectures that are computationally error-tolerant are therefore urgently needed. This paper systematically leverages the properties of Redundant Residue Number Systems(RRNS) by varying the number of non-redundant (n) and redundant (r) residues. First, we propose a scalable RRNS microarchitecture that simultaneously supports both, error-correction, as well as checkpointing&restart capabilities. Second, we design novel RRNS-based adaptive checkpointing&restart mechanisms that automatically guarantee reliability while minimizing the energy-delay product(EDP). To the best of our knowledge, these are the first set of checkpointing mechanisms targeting the RRNS infrastructure. Moreover, these mechanisms optimize the usage efficiency of memory capacity. Third, we systematically explore the RRNS design space to find the best (n, r) configuration point. For similar reliability when compared to a conventional binary core, the proposed RRNS scalable microarchitecture reduces EDP by 53% on average for memory-intensive workloads and by 67% on average for non-memory-intensive workloads.

Sparse data applications have irregular access patterns that stymie modern memory architectures. Although hyper-sparse workloads have received considerable attention in the past, moderately-sparse workloads prevalent in machine learning applications, graph processing and HPC have not. Where the former can bypass the cache hierarchy, the latter fit in the cache. This article makes the observation that intelligent, near-processor cache management can improve bandwidth utilization for data-irregular accesses, thereby accelerating moderately-sparse workloads. We propose SortCache, a processor-centric approach to accelerating sparse workloads by introducing accelerators that leverage the on-chip cache subsystem, with minimal programmer intervention.

In this issue, we take a look at quantum computing: what has been accomplished and what is its future. We present a collection of views about the realistic challenges facing the future of quantum computing.

Logic-memory integration helps mitigate the von Neumann bottleneck, and this has enabled a new class of architectures that helps accelerate graph analytics and operations on sparse data streams. These utilize merge networks as a key unit of computation. Such networks are highly parallel and their performance increases with tighter coupling between logic and memory when a bitonic algorithm is used. This paper presents energy-efficient on-chip network architectures for merging key-value pairs using both word-parallel and bit-serial paradigms. The proposed architectures are capable of merging two rows of high bandwidth memory (HBM)worth of data in a manner that is completely overlapped with the reading from and writing back to such a row. Furthermore, their energy consumption is about an order of magnitude lower when compared to a naive crossbar based design.

Josephson junctions, cryogenic CMOS, and adiabatic circuits were proposed as computing options decades ago, but never got traction due to competition from room-temperature CMOS. However, quantum computer control electronics naturally requires cryogenic temperatures, making a deeper investigation of these technologies timely.We argue that a technology hybrid and new system design principles are needed, which we illustrate with adiabatic cryo-CMOS circuits playing an unanticipated but very important role.Transistor redesign will lead to even further improvement beyond what’s illustrated in this paper, but more research will be needed to know how much.