A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin bit efficiency is achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 data using a low-power encoding logic and an output driver. The receiver achieves a bit error rate (BER) of less than 1E-12 over an 80-mm FR-4 printed circuit board (PCB) channel. At the maximum data rate, the bit efficiency of the transceiver is 1.11 pJ/bit, consuming 33.4 mW. In the receiver, the attenuated PAM-3 data are equalized by a continuous-time linear equalizer (CTLE) and a one-tap tri-level DFE, which has the same complexity as that of non-return-to-zero (NRZ) signaling. The tri-state buffers, which have a floating PMOS switch, convert the output of the comparator into NRZ data, resulting in reduced delay and power dissipation. Four channels of the transceivers operate at data rates of up to 30 x 4 Gb/s, and the horizontal eye margin of the measured PAM-3 data is achieved at a UI of 0.14 for the PRBS-7 pattern at the maximum data rate.

The exponential increase in demand for global energy intake in day-to-day life directs us to look for a green and cost-effective energy generation and storage alternative. India being a fastly developing nation with a vast population, requires the alternative energy resource to meet up the energy deficit in an eco-friendly manner and be self-reliant in energy demands. This review aims to compile and assess developments in energy materials research from Indian prospects. Therefore, this paper discusses India’s energy scenario by understanding the fundamental concepts and developments of various solar cell technologies and an overview of energy storage systems (batteries and supercapacitors), accentuating the research progress made so far along with future possibilities. This exploratory study reviews the systematic and sequential advances in all three generations of the solar cell, i.e. Si solar cell, thin-film solar cell, dye-sensitized solar cell, and perovskite solar cells. Herein, the discussion is directed at developing novel materials that are efficient, stable, and economical. Moreover, the current status of the high-performance devices for each technology is reviewed in detail. Finally, the prospects, areas of improvement, and future trends in developing cost-effective and efficient energy materials for solar cells and storage devices are highlighted.

This study reports on the synthesis and characterization of a novel electrode material for supercapacitor applications based on a clustered heterostructure of indium sulfide (In₂S₃) and single-walled carbon nanotubes (SWCNTs). The In₂S₃-SWCNT (INSC) sample was prepared using the facile successive ionic layer adsorption and reaction (SILAR) method and demonstrated a higher specific capacitance (258 Fg⁻¹ at 1 Ag⁻¹) compared to the bare indium sulfide (In₂S₃) electrode. The enhanced electrochemical performance is attributed to the synergistic effect between the In₂S₃ and SWCNTs, which improves electron transportation, catalytic nature, and specific capacitance. Moreover, the cyclic stability of the INSC electrode was significantly improved, retaining 96.8% of the initial capacitance after 3000 cycles. The high voltage holding capacity and high cyclic efficiency of the fabricated INSC-based supercapacitor devices suggest their potential for next-generation energy storage devices. Additionally, the INSC electrode-based supercapacitor devices exhibit excellent flexibility and bendability, retaining similar performance even at a bending angle of 180°, making them suitable for flexible energy storage applications.

This paper presents a segmented match-line (ML) and charge-sharing based search scheme for low-cost ternary contents addressable memory (TCAM). In the proposed TCAM, a first-round search operation is performed on half cells located in even columns. During the first-round search, most of the mismatch cases are filtered out while remaining few mismatched cases that is misrecognized as the matched case. To complete the search operation in a low-power manner, a charge-sharing between the segmented MLs is used for the second-round search operation. The proposed 16KB 16T-NOR TCAM macro has been implemented using a 28nm CMOS technology. Numerical results show that the proposed TCAM improves sensing delay up to 5.6x faster and saves search energy-delay-product by 83% compared to the conventional approaches.

A point-to-point interface with a clock embedded scheme (CES) in Fig. 29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery in RX without a reference clock channel is usually carried out using one of two type of data encoding schemes, embedded clock with dummy clock bits [1–2,5] or ensured transition density with data encoding such as 8B10B encoding [3]. However, these two schemes reduce the effective bandwidth because they require over 20% overhead in the data stream. Although highly efficient signaling schemes have been introduced recently in the literature [4] to cope with the physical limitations of the process and channel, it is difficult to adopt these multi-level signaling schemes in intra-panel interfaces where there is a highly resistive channel of Chip-On-Glass and a ground bouncing problem [5] due to different voltage domains (1V and 8V–30V) for serial link and source drivers. This paper introduces a braid clock signaling (BCS) scheme which has the following advantages: 1) clock information without redundant bits; 2) NRZ signal levels for high voltage margin; and 3) low EMI emission with a random data dependent encoding and a spread transition scheme.