Through silicon via (TSV) is a key enabler for 3D integration technology to provide high-density and high-speed transmission channels. However, the serious defects including open circuit and short circuit will result in functional failure. In this paper, a method to identify the open and short defect and detect the defect position is developed based on machine learning approach. Taking S parameters as training dataset, the predictive model is trained and evaluated, the performance of models based on bagging method and boosting method are compared. The results demonstrate the predictive model could correctly classify the defect type and predict the defect position accurately.

In modern systems-on-chip, cryptographic coprocessors bring more flexibility to design, not only accelerating the encryption process but also compressing design resources by sharing algorithm units. A high- performance unified coprocessor for AES-128 and SM4 encryption is proposed in this paper. On the one hand, based on the similarities between the two types of algorithms, the multiplicative inverse (MI) unit of the Sbox is realized in the composite field, and by sharing the reconfigurable Sbox logic (RCSL), the hardware resource consumption of circuits compatible with both algorithms is reduced. On the other hand, global pipeline technology based on shared-RCSL is used to improve the throughput of the coprocessor. In TSMC 65nm 1.08V CMOS technology, compared to the synthesized results of independently AES-128 and SM4, the area and power at 500MHz of the unified coprocessor are reduced by 42% and 43%, respectively.

In this paper, modeling for TSV pair structures with void defects, pinhole defects and open defects by using an electromagnetic full wave analysis tool is presented. A low-bandwidth equivalent lumped circuit model of above TSV structures are extracted to analyze the effects of different defect sizes and different defect locations. The simulation results show void defects only minimally affect the TSV resistance. And, the lumped circuit model and scattering parameter are changed by open defects which cut off the TSV completely. Besides, the pinhole of a TSV significantly change the equivalent coupling capacitance between TSV pair. Based on these results, some appropriate testing methods are discussed.

With the arrival of the 5G era, IoT develops and promotes rapidly and the security issues of IoT are concerned increasingly. SHA256 and SM3 are significant hash encryption algorithms that can improve the security of IoT systems. This paper proves the equivalence between partial Boolean functions of these two encryption algorithms and designs a shared security encryption circuit that can support SM3 and SHA256 modes. Compared with the traditional design, the area of this design decreases by 17.3%. To improve the speed and reduce power consumption, this design is optimized by precomputation and reducing the signal update frequency. The precomputation part shortens the critical path and increases the maximum frequency and throughput successfully. The power optimization part also improves energy efficiency. After function verification, this design can encrypt the original message correctly and efficiently and is synthesized based on the 65nm LVt process library of SMIC.

Ultra-high density 2.5/3D heterogeneous integration has been considered an essential solution for rebooting computation applications like high performance computing, machine learning, and brain-mimicking neuromorphic computing, in both cloud and edge modes. Interposers with active auxiliary circuitry such as tunable power distribution network (PDN), phase locked loops, active signaling equalizers/ buffers, and even neuromorphic units, are emerging as much more attractive and flexible platforms than passive interposers for these applications. In this paper, an active interposer conception acting as a platform for heterogeneous integration of logic, memory and neuromorphic computing circuits, is proposed for rebooting computation purpose, featuring functioning units such as active PDN, data switching and signal conditioning circuits, and neuromorphic units based on so-called neural TSVs. New features such as pulse operation of neuron circuit and high speed data switching may induce new power integrity issues. Fortunately, the introduction of neural TSVs with large capacitance may also acting as the in-situ decoupling capacitors whose value can be modulated by the switching on/off of the MOSFETs associated with the neural TSVs in the same neuron cell, and thus a compact and tunable PDN can be constructed, whose impedance and anti-resonance characteristics may be reconfigured flexibly for an optimal power distribution and minimal simultaneous switching noise. Principles are disclosed and compact circuit modeling is set up for the PDN. Circuit and full-wave simulation results are demonstrated, confirming the conception and its effectiveness.