The sixth generation (6G) mobile communication networks are expected to intelligently integrate into various aspects of modern digital society, including smart cities, homes, health-care, transportation, and factories. While offering a multitude of services, it is likely that societies become increasingly reliant on 6G infrastructure. Any disruption to these digital services, whether due to human or technical failures, natural disasters, or terrorism, would significantly impact citizens’ daily lives. Hence, 6G networks need not only to provide high-performance services but also to be resilient in maintaining essential services in the face of potentially unknown challenges. This paper provides a general review of the state of the art on resilient systems, definitions, concepts, and approaches. Moreover, it introduces a comprehensive concept, i.e., resilience-by-design (RBD), in three different levels for designing resilient 6G communication networks, summarizing our initial studies within the German Open6GHub project. First, we outline the general RBD enabling principles and discuss their related sub-categories. Next, adopting an interdisciplinary approach, we propose to embed these principles across all 6G layers/perspectives including electronics, physical channel, network components and functions, networks, services, and cross-layer and cross-infrastructure considerations and discuss their challenges. We further elaborate the RBD principles and their realizations along with several 6G use-cases. The paper is concluded by presenting a comprehensive list of open problems for future research on 6G resilience.

Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( $32.4\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$ ) to ( $62.5\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$ ), depending on the variant.

An experimental study has been conducted to evaluate the feasibility of a current mode gamma radiation dosimeter, consisting of a commercial PIN photodiode as a radiation sensor, and a custom made auto-ranging electrometer for real-time measurement of the PIN photodiode?s response under radiation exposure. The radiation induced direct current response for single PIN photodiodes with different active areas, as well as for multiple PIN photodiodes connected in parallel, has been investigated. Three types of commercial silicon PIN photodiodes have been chosen for evaluation - S1223, BPW34, and PS100-6-CER2 PIN. During the experiment, five samples have been tested - three samples made of single PIN photodiodes (one sample of each photodiode type) and two samples formed by connecting multiple photodiodes in parallel (two BPW34 photodiodes in parallel and four BPW34 photodiodes in parallel). The samples have been irradiated with a 60Co gamma ray source and the relations between the induced photocurrent and the dose rate, and between the accumulated charge and the absorbed dose, have been determined. For measuring the photodiodes response, a custom made auto-ranging electrometer controlled by a personal computer, and capable of measuring direct currents from 50 pA to 10 mA with relative error less than 2.5%, has been used. Obtained results have shown very good linearity between the dose rate and the induced photocurrent for dose rates ranging from 0.93 Gy/h to 67 Gy/h. Also, very good linearity has been observed between the accumulated charge and the absorbed dose for all tested samples, within the investigated range of absorbed doses from 472 mGy to 3.3 Gy. On the basis of the obtained results, a simple model has been derived, enabling the estimation of the photodiode?s current response as a function of the dose rate and the photodiode?s geometry (active area and depletion layer width).

The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels.

Convolutional Neural Networks (CNNs) have revolutionized many applications in recent years, especially in image classification, video processing, and pattern recognition. This success of CNNs has been a motivating factor for solving even more complex problems involving multiple data modalities. Traditionally, a single CNN accelerator has been optimized for just one task or has been used to perform correlated tasks. We leverage the CNNs capability to learn patterns and use one accelerator to perform multiple uncorrelated tasks from different modalities and achieve an average accuracy above 90%, which would otherwise require three accelerators. Two types of CNN architectures (i.e., fused and branched) are evaluated for three distinct tasks based on accuracy, quantization, pruning, hardware resource utilization, power, and latency. Capitalizing on this, we have further proposed a runtime reconfigurable CNN accelerator supporting fault-tolerant (FT), high-performance (HP), and de-stress (DS) modes.

Recently the conservative space industry driven by the requirements of novel applications decided to introduce multiprocessor systems. Following the same line of motivation we introduce the PISA multiprocessor chip with improved power robustness for space applications which is successfully produced and tested in IHP 130 nm technology. The paper brings several novelties in respect to the current state-of-the-art. The chip uses the Waterbear framework in which the multiprocessor cores can be dynamically put in one of three different operating modes according to the current application requirements regarding performance, power consumption and fault tolerance. The chip has special power supply architecture with 13 power domains and Adaptive Voltage Scaling (AVS) mechanism based on voltage regulators which imposes a non-standard IC design flow. The measurement results showed that the power supply of the multiprocessor cores can be reduced from the nominal 1,2 V downto 0,82 V without compromising power integrity.