In 3D packaging memory devices, solder joints are critical links between the chip and the printed circuit board (PCB). Under severe working conditions, cracks inevitably occur due to thermal shock. If cracks grow in the solder joint, the chip will be disconnected with the PCB, causing its function failure. In this paper, the reliability of solder joints under thermal shock are evaluated for 3D packaging memory devices by means of the SEM and finite element analysis. As microscopically studied by the SEM, it is found out that the main failure mechanism of solder joints in such test is the thermal fatigue failure of solder joints. Finite element analysis shows that cracks are caused by the accumulation of plastic work and creep strain. The initiation and growth of cracks are mainly influenced by the inelastic strain accumulation. The trends of cracks are influenced by the difference between the coefficient of thermal expansion (CTE) of epoxy resin and that of the chip.

With the advancement of micro- and nanomanufacturing technologies, electronic components and chips are increasingly being miniaturized. To automatically identify their packaging materials for ensuring the reliability of ICs, a hybrid deep learning framework termed as CNN–transformer interaction (CTI) model is designed on IC packaging images in this paper, in which several cascaded CTI blocks are designed to bidirectionally capture local and global features from the IC packaging image. Each CTI block involves a CNN branch with two designed convolutional neural networks (CNNs) for CNN local features and a transformer branch with two transformers for transformer global features and transformer local-window features. A bidirectional interaction mechanism is designed to interactively transfer the features in channel and spatial dimensions between the CNNs and transformers. Experimental results indicate that the hybrid framework can recognize three types of IC packaging materials with a good performance of 96.16% F1-score and 97.92% accuracy, which is superior to some existing deep learning methods.

This study focuses on the evaluation of electrical stress limit capability for 3D-packaged memory (256 M × 72-bit DDR3 SDRAM) (Shanghai Fudan Microelectronics Group Co., Ltd., Shanghai, China). Guided by Reliability Enhancement Theory, this study presents a meticulously designed comprehensive test profile that incorporates critical stress parameters, including supply voltage, input clock frequency, electrostatic discharge (ESD) sensitivity, and electrical endurance. Explicit criteria for stress selection, upper/lower bounds, step increments, and duration are established. A dedicated test platform is constructed, integrating automated test equipment (ATE) and ESD sensitivity analyzers with detailed specifications on device selection criteria and operational principles. The functional performance testing methodology is systematically investigated, covering test platform configuration, initialization protocols, parametric testing procedures, functional verification, and acceptance criteria. Extreme-condition experiments—including supply voltage margining, input clock frequency tolerance, ESD sensitivity characterization, and accelerated electrical endurance testing—are conducted to quantify operational and destructive limits. The findings provide critical theoretical insights and practical guidelines for the design optimization, quality control, and reliability enhancement of 3D-packaged memory devices.

Glass-insulated terminals (GITs) are widely used in high-reliability microelectronic systems, where glass fall-offs in the sealing region may seriously degrade the reliability of the microelectronic component and further degrade the device reliability. Automatic inspection of such defects is challenging due to strong light reflection, irregular defect appearances, and limited defective samples. To address these issues, a coarse-to-fine machine-learning framework is proposed for glass fall-off detection in GIT images. By exploiting the circular-ring geometric prior of GITs, an adaptive sector partition scheme is introduced to divide the region of interest into sectors. Four categories of sector features, including color statistics, gray-level variations, reflective properties, and gradient distributions, are designed for coarse classification using a gradient boosting decision tree (GBDT). Furthermore, a sector neighbor (SN) feature vector is constructed from adjacent sectors to enhance fine classification. Experiments on real industrial GIT images show that the proposed method outperforms several representative inspection approaches, achieving an average IoU of 96.85%, an F1-score of 0.984, a pixel-level false alarm rate of 0.55%, and a pixel-level missed alarm rate of 35.62% at a practical inspection speed of 32.18 s per image.