With the development of science and technology, consumers’ requirements for various electronic devices present a trend of more diverse functions and thinner bodies. This makes integrated circuits mounted in electronic products and their packaging more vital to satisfying the above requirements. Ball grid array (BGA) packaging is widely used in the field of microelectronic manufacturing industries due to its multiple I/O volumes and excellent electric characteristics. However, due to environmental loads such as vibration and impact during its production and application, defects inevitably emerge in BGA solder joint defects, which will lead to the failure of electronic products. This article summarizes the state-of-the-art research on the factors, analysis methods, and models for the fatigue failure of BGA chips. After rigorous discussions concerning this research, some theoretical suggestions are provided for BGA packaging in reliability analysis and the establishment of evaluation standards.

In 3D packaging memory devices, solder joints are critical links between the chip and the printed circuit board (PCB). Under severe working conditions, cracks inevitably occur due to thermal shock. If cracks grow in the solder joint, the chip will be disconnected with the PCB, causing its function failure. In this paper, the reliability of solder joints under thermal shock are evaluated for 3D packaging memory devices by means of the SEM and finite element analysis. As microscopically studied by the SEM, it is found out that the main failure mechanism of solder joints in such test is the thermal fatigue failure of solder joints. Finite element analysis shows that cracks are caused by the accumulation of plastic work and creep strain. The initiation and growth of cracks are mainly influenced by the inelastic strain accumulation. The trends of cracks are influenced by the difference between the coefficient of thermal expansion (CTE) of epoxy resin and that of the chip.

During reflow soldering, voids inevitably emerge inside the solder joints of chip resistors, which will influence the reliability of the electronic device. In this paper, an adaptive hybrid framework is proposed for multi-scale void inspection of chip resistor solder joints. First, an adaptive partition scheme is proposed to adaptively divide the image of the chip resistor solder joint into two regions, which correspond to the solder beneath the chip resistor body (Region 1) and the solder fillet (Region 2). Then, the voids in the two regions are separately inspected by two proposed adaptive inspection methods. One is that the multi-scale convolution with adaptive circular kernels, guided filtering, and thresholding segmentation is proposed to inspect the voids in Region 1. The other is that an improved active contour model is proposed to inspect the voids in Region 2, which incorporates the gray adaptive strategy and shape prior of the void. Finally, the shape factor and average gray strategy are utilized for void fine inspection of the chip resistor solder joint. Experimental results indicate that the proposed framework is superior to some existing methods, with an inspection performance of 0.9069 average Dice coefficient, 0.9907 F1 Score, and 98.51% Accuracy at a reasonable inspection speed.

As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.

Voids in ball grid array (BGA) solder joints have been considered as a main problem in lead-free soldering process. Compared with tin-lead solder, worse wetting capability of lead-free solder aggravates the formation of voids. Along with the wide application of BGA packages and the transition of lead-free soldering, the effect of voids on the reliability of BGA solder joints has been concerned. In this paper, a 3D strip model of lead-free BGA mounted at PCB with coarser mesh is developed and analyzed under accelerated temperature cycling condition(-25 °C _~100 °C) firstly. According to the principle of strain failure, the critical solder joint is identified. Then, five kinds of voids are designed in critical solder joint and the submodels with refined meshes are established and analyzed respectively. The results show that the effect of voids on thermal fatigue reliability of solder joints has a double characteristic. When the void located at the initial maximum stress region, the accumulation of creep strain is aggraved, this kind of voids have negative effect on the thermal fatigue reliability of solder joints. In case of voids at the center of solder joints, even if the voids areas is 25% of solder joint section, the creep strain still is smaller than the solder joints without void. At last, in case of voids away from the initial maximum strain region, the effevt of void on the thermal fatigue reliability of solder joints is no obvious.

Integrated circuit (IC) X-ray wire bonding image inspections are crucial for ensuring the quality of packaged products. However, detecting defects in IC chips can be challenging due to the slow defect detection speed and the high energy consumption of the available models. In this paper, we propose a new convolutional neural network (CNN)-based framework for detecting wire bonding defects in IC chip images. This framework incorporates a Spatial Convolution Attention (SCA) module to integrate multi-scale features and assign adaptive weights to each feature source. We also designed a lightweight network, called the Light and Mobile Network (LMNet), using the SCA module to enhance the framework’s practicality in the industry. The experimental results demonstrate that the LMNet achieves a satisfactory balance between performance and consumption. Specifically, the network achieved a mean average precision ($mA{P}_{50}$) of 99.2, with 1.5 giga floating-point operations (GFLOPs) and 108.7 frames per second (FPS), in wire bonding defect detection.