With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4 $\mathsf{\mu }$m${}^2$. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm${}^2$.

Recently, the concept of the difference and sum coarray has attracted increasing interest in the direction of the arrival estimation field because it can generate enhanced degrees of freedom. In this paper, we propose an improved transformed nested array design strategy by relaxing the constraints on the dense subarray of the transformed nested array. Then, three conditions are given for the array design to ensure the continuity of the difference and sum coarray. Based on the strategy, we develop a novel nested configuration named coprime transformed nested array (CTNA) whose dense subarray is a coprime structure, and the closed-form expressions for the sensor positions and the range of consecutive coarray are derived. CTNA can increase the number of degrees of freedom (DOFs) compared to the existing nested arrays, while the mutual coupling effect can be maintained at the same low level as the coprime arrays, which indicates that CTNA has the merits of both nested array and coprime array. Numerical simulations are performed to verify the superiority of the proposed array configuration in terms of the number of DOFs, mutual coupling and direction of arrival (DOA) estimation accuracy.