This paper introduces a novel speed-oriented architecture of point multiplication in ECC (Elliptic Curve Cryptography). A balanced full-precision multiplier is proposed to shorten latency, and a new modular inversion architecture is integrated to reduce the total number of clock cycles in point multiplication. A modified Montgomery Ladder Algorithm that takes three clock cycles to calculate one input bit is proposed to best utilize hardware resources. A mixed-pipeline technique is used to balance delay of different paths and increase frequency. The proposed architecture is implemented on GF(2163) and GF(2571), based on Xilinx Virtex-5 and Virtex-7 FPGA. For GF(2163), the design reaches 211 MHz, with 29309 LUTs, and 547 clock cycles or 2.6 μs latency on Virtex-5; 320.5 MHz, with 28911 LUTs and 1.7 μs latency on Virtex-7. For GF(2571), the design reaches 186 MHz, with 286400 LUTs, and 1813 clock cycles or 9.6 μs latency on Virtex-5; 267 MHz, 290001 LUTs and 6.79 μs latency on Virtex-7. The proposed design achieves the lowest latency among all existing works, and its performance is also among the top. Furthermore, it is demonstrated that the proposed architecture maintains high speed for larger binary fields, making it more suitable to be implemented in large-bit-length platforms with higher security level. Since the multiplier and its segments work in different bit-length and refer to different fields, the proposed architecture can also be upgraded to a reconfigurable design to support multiple-field point multiplication in the future.

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2 ⁵⁷¹ ) and GF(2 ²⁸³ ) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2 ⁵⁷¹ ), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2 ²⁸³ ) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4 $\mathsf{\mu }$m${}^2$. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm${}^2$.

Since entering the era of big data, the degree of information sharing is getting higher and higher; the information exchange is becoming more and more convenient, but at the same time, personal information is also easy to be exposed to the network environment, if it is used by criminals to lead to information leakage, and then bring certain risks. Therefore, it is in the information age and do a good job of network information security and confidentiality. At present, the security and secrecy of network information are mainly realized by cryptography. Public key cryptography can encrypt information and ensure the security of information transmission, so it is widely used in the contemporary society. At present, elliptic curve encryption is highly respected in the research field of public key cryptosystem. Elliptic curve encryption is divided into two main points, multiplication and inversion, respectively. Through the comparison of these two algorithms, it can be found that there are several choices if the main research objective is to save time, and the Euclidean extension method is mainly discussed in this paper. In other words, more efficient algorithms are used in the hardware implementation process, and a variety of algorithms can be used instead of a single curve algorithm. In this process, we can find the special features of upper level operation and bottom level finite operation. The upper level operation is KP operation, while the bottom level operation is fast calculation of four kinds of in finite field operation, and finally realize FPGA algorithm. With the help of Quartus ii developed by predecessors, the upper and lower operations of elliptic curve are carried out using VHDL language. Combined ANXIX9.62 in the elliptic curve of each module to test, so as to ensure the accuracy of the data, reduces the error. According to the test results, the designed chip can efficiently complete the elliptic curve encryption system in the whole process. And the average KP operation time can reach 15.15 ms at 20 MHz frequency. At the same time, the chip can complete the operation on ECC public key with any variable curve in domain less than 256. Therefore, this chip is a high-speed elliptic curve cryptographic chip with optional system parameters. Based on this, this article on the elliptic curve encryption algorithm based on FPGA hardware implementation of system design, from the view of mathematical study analysis, was carried out on the elliptic curve cryptosystem, according to the above two big difficulty, namely, the polynomial of GF(2), the finite field multiplication, and inversion; there will be a detailed studies of discussion, through software comparison to find the differences between different software, especially the software implementation performance level. In addition, it will also focus on the design of elliptic curve algorithm PGA, so as to explore the solution of the algorithm hardware.

Stacked DRAM used as the last-level caches (LLCs) in multicore systems delivers performance enhancement due to its capacity benefit. While the performance of LLC depends heavily upon its block replacement policy, the conventional replacement policy needs redesigning to exploit the best of DRAM cache and avoid its drawbacks. The existing DRAM cache insertion policy blindly forwards victim lines replaced from L3 to the off-chip memory, regardless of the potential for increased hits by placing a fraction of them in the DRAM cache. Nevertheless, a naïve design that steers all dirty victims to the DRAM cache introduces excessive writeback traffic, which aggravates capacity misses and DRAM interference. To leverage insertions in terms of writeback or fill requests, we propose a collective writeback and fill policy that adapts to the distinct access patterns of heterogeneous workloads based on runtime misses and writeback efficiency. The synthesis result shows that the new policy has only a small hardware overhead. According to the experimental results on the gem5 simulator, the new policy increases harmonic instruction per cycle throughput by 18%, 11.6%, and 11.7%, respectively, compared with the Always Writeback (AW)-Always Fill policy, Never Writeback Adaptive DRAM Placement policy, and AW Adaptive DRAM Placement policy on 64-MB alloy cache, while the improvement is 19.3%, 13.7%, and 14.5% on 64-MB MissMap cache.

The modal parameters of the Robert A Memorial Millikan Library (referred to Millikan Library) building are estimated with forced vibration test techniques using various different instruments. The 10-story building is a reinforced concrete structure and permanently instrumented with a sensor array of 36-channel Force-Balanced accelerometers (referred to FBA) and two digital recorders primarily to monitor the building dynamic response during earthquakes. Three different tri-axial Micro-Electro Mechanical System (referred to MEMS) accelerometers were also deployed to measure the building response at the basement floor, at 5th floor, and at 9th floor during forced vibration testing. The amplitudes of the responses measured are compared in time domain. Whether the first two fundamental periods can be identified is mainly considered in frequency domain. SNR (abbreviation for Signal to Noise Ratio) is introduced to determine the data quality by fitting a sine function to recorded data. Amplitude characteristic analysis indicates that signal recorded from MEMS accelerometers shows occasional spikes. At low intensity shaking signal amplitudes tend to be equal and amplitude from MEMS is almost always higher than that from FBA. At higher amplitudes, amplitude mismatch becomes larger. The first two fundamental periods of the building in North-South and East-West directions can be clearly distinguished in frequency domain from the response signals recorded by FBAs. Responses recorded by MEMS accelerometers are in higher chaos at the basement floor and visual detection of fundamental frequencies of the building is infeasible The SNR computed for 9th floor response is larger than that of the basement floor response. That indicates that low amplitude response contains more noise than relatively higher response. For the same floor, the SNR computed for the response measured by FBA is always larger than those of responses measured by three MEMS accelerometers. Therefore, MEMS accelerometers should be applied for structural health monitoring with caution when ambient data is of concern.