Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits. However, its FPGA implementation has a poor reliability, and error correction codes (ECCs) are usually needed to eliminate the noise in the responses, which incur additional high hardware overhead and require NVM for helper data storage. In this paper, we present a highly reliable arbiter PUF with improved uniqueness using the bit-self-test (BST) strategy. A delay detection circuit is added into a classical arbiter PUF to test the delay deviation that produces each bit of the PUF response in real-time and mark the response as reliable using a reliability flag when the delay deviation is significantly more than a predefined threshold. Then, the robust responses can be used. We implemented the BST-arbiter PUF on a Xilinx Artix 7 FPGA. The test results show that the selected responses achieve outstanding performance where the bit error rate is less than 10 ^-9 , the bias is 50.3%, and the uniqueness is 49.1%. Thus, the BST-APUF, which drastically reduced the ECC overhead, can be applied to lightweight cryptography applications.

This paper presents a highly reliable and invasive-attack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge-response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled by an SC circuit and further amplified by a latch-styled sense amplifier. By covering the entire chip with the metallic transmission lines connected to the sampling capacitor, the PUF can resist invasive attacks. To provide highly reliable responses, a built-in self-test (BIST) strategy is also adopted. A test capacitor is embedded in the PUF circuits to automatically test the capacitance deviation of the SC circuit. Only when the capacitance deviation is large, the output of the PUF is selected for use. The proposed strong SC PUF circuit is fabricated and verified using HJ standard 0.18-μm CMOS process. Measured results show that after using the BIST strategy, the bit error rate is less than 10⁹ when the ratio of the selected responses is 19.6% for the PUF instances in our test.

The primary task of wireless sensor networks (WSNs) is to collect various types of data, for example, weather data, traffic data, etc. Collected data in WSNs are different from most data transmitted in digital communication applications. Most collected data in WSNs contain only few bits of information, but most data in data communication applications contain a large number of bits. All existing data encryptions in WSNs use conventional symmetric-key encryptions (e.g., advanced encryption standard (AES)) in which each large-size key is used to encrypt a block of large-size of data (e.g., a fixed block size of 128 bit in AES), and the security is based on a large-size of pairwise shared key (e.g., 128/192/ 256 bits in AES) between the sender node and the receiver node. Obviously, these conventional encryptions are not suitable for WSNs since the size of keys are much larger than the size of data. We propose a novel data encryption, in which it encrypts only few bits of data, and the security is based on multiple pairwise shared keys with short length. The encryption speed is much faster than conventional symmetric encryptions. Data aggregation is an efficient way to transmit data in a network. In the past, most encrypted data aggregations were designed based on public-key based homomorphic encryption. Public-key encryptions need time-consuming computation, so these schemes are not suitable for applications in WSNs. Most data in WSNs are routed through a path from the source node to the receiver node, which involves multiple sensor nodes. Our encrypted data aggregation is also called path-oriented data encryption. When multiple data are collected in WSNs, our scheme allows sensors in the path to aggregate all collected data in a piggyback ride. Our proposed encrypted data aggregation is a lightweight solution, which is suitable for applications in WSNs.

Once there are constant or infrequently changed bits (COIBs) in two adjacent input messages of SHA-2, the switching power of input messages data registers (IMD-REGs) used for COIBs will disappear. Meanwhile, when full pipeline SHA-2 is applied in a certain application scenario where the IMD-REGs used for COIBs can be removed, more area of full pipeline SHA-2 can be saved as the proportion of IMD-REGs in message word registers increases. This paper proposes a new message expansion structure for full pipeline SHA-2 to increase the proportion of IMD-REGs. By inserting two expanders in last part of expansion structure pipeline stages and rescheduling the expander, the consumption rate of input messages will be decreased and the proportion of IMD-REGs will be increased. Compared with normal message expansion structure, the ratio of IMD-REGs to total message word registers in the proposed structure is increased from 15.1% to 41.6% for full pipeline SHA256, and 11.2% to 32.4% for full pipeline SHA512. When COIBs exists in adjacent input messages, the power and area advantages of proposed new message expansion structure have been demonstrated by FPGA and ASIC implementations.

Dempster-Shafer (D-S) evidence theory is regarded as an effective method of dealing with the uncertainty of the information but still suffers from the conflict problem among the evidence. Despite that various techniques were presented in plenty of publications, currently, there is no convincing evidence and firm conclusion about the optimum solution. This study presents Belief Coulomb Force (BCF) into D-S evidence theory, where Zhou et al. entropy is applied to represent the electrical charge of the belief function, and the Coulomb gravity or repulsion would be identified with the Pearson correlation coefficient. According to the simulation results, the recognition accuracy on malfunction diagnosis of the presented approach reaches 93.7%, and the effectiveness of analyzing the conflict evidence problem can be demonstrated from the comparison with the previous methods.

By sensing and changing the parasitic capacitance mismatch of chip pads, bumps or bonding wires, package substrate and balls, and printed circuit board (PCB) solder joints and traces into on-chip keys, the proposed chip-PCB hybrid switched-capacitor (SC) physical unclonable function (PUF) can detect the capacitance alteration caused by damaging of the package or removing of the chip from the original PCB, thereby achieving the anti-desoldering and depackaging-attack protection for the security chip. Moreover, the IO ports used for connecting the PCB traces can be shared with other normal communication function blocks, which can realize full use of IO resources while not increasing the package cost. The proposed chip-PCB hybrid SC PUF is verified in security chips by using different processes, including the traditional 28-nm CMOS process and the advanced 14- and 7-nm FinFET CMOS processes. The change of chip-PCB hybrid SC PUF’s output key when the bump of the chip is removed, or the chip is desoldered from the original PCB verifies the anti-desoldering and depackaging-attack properties of the proposed chip-PCB hybrid SC PUF. With the help of chip-PCB hybrid SC PUF, the comprehensive protection of the overall hardware environment for both the chip and the PCB hardware systems can be realized.