This paper presents a highly reliable and invasive-attack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge-response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled by an SC circuit and further amplified by a latch-styled sense amplifier. By covering the entire chip with the metallic transmission lines connected to the sampling capacitor, the PUF can resist invasive attacks. To provide highly reliable responses, a built-in self-test (BIST) strategy is also adopted. A test capacitor is embedded in the PUF circuits to automatically test the capacitance deviation of the SC circuit. Only when the capacitance deviation is large, the output of the PUF is selected for use. The proposed strong SC PUF circuit is fabricated and verified using HJ standard 0.18-μm CMOS process. Measured results show that after using the BIST strategy, the bit error rate is less than 10⁹ when the ratio of the selected responses is 19.6% for the PUF instances in our test.

This Letter proposes a reliable and lightweight key generator based on a novel bit‐self‐test arbiter physically unclonable function (BST‐APUF). The BST‐APUF adds a delay detection circuit into a classical APUF to automatically test the delay deviation that produces each bit of the PUF response and generates a reliability‐flag for each response to indicate its reliability. The key generator collects robust responses and produces a secure key using a cryptographic entropy accumulator. FPGA implementation results show that the overhead and the helper data length of the authors proposed key generator are significantly lower than that of the state‐of‐the‐art schemes when generating a 128‐bit key with a bit error rate of 10 ⁻⁹ .

Once there are constant or infrequently changed bits (COIBs) in two adjacent input messages of SHA-2, the switching power of input messages data registers (IMD-REGs) used for COIBs will disappear. Meanwhile, when full pipeline SHA-2 is applied in a certain application scenario where the IMD-REGs used for COIBs can be removed, more area of full pipeline SHA-2 can be saved as the proportion of IMD-REGs in message word registers increases. This paper proposes a new message expansion structure for full pipeline SHA-2 to increase the proportion of IMD-REGs. By inserting two expanders in last part of expansion structure pipeline stages and rescheduling the expander, the consumption rate of input messages will be decreased and the proportion of IMD-REGs will be increased. Compared with normal message expansion structure, the ratio of IMD-REGs to total message word registers in the proposed structure is increased from 15.1% to 41.6% for full pipeline SHA256, and 11.2% to 32.4% for full pipeline SHA512. When COIBs exists in adjacent input messages, the power and area advantages of proposed new message expansion structure have been demonstrated by FPGA and ASIC implementations.

By using metal blocks as the protective coating, placing the sensitive signals in last but second metal (LSM), integrating a low-cost one-time programming (OTP) cell in each PUF unit, the proposed switched-capacitor (SC) PUF can both provide sensitive anti-invasive-attack protective coating and stable key for the security chip. Moreover, the circuit parameters and the layout implementation of the SC PUF unit are all compatible with other digital standard cells, which greatly facilitates the integration of SC PUF unit in the security chip by using digital design flow when its function, timing, power, and layout views are characterized using commercial timing and layout extraction tools. The anti-invasive-attack ability, stability, and digital design flow compatibility of the proposed SC PUF standard cell are verified in a security chip by using a standard 0.18- μm CMOS process. The measured bit error rate, bias, average intra-die HD, and average inter-die HD of output keys after OTP is <; 10 ^-4 , 46.72%, 0%, and 50.38% respectively. Finally, the failed probing and destruction attack attempts to the coating also verify the invasive-attack-resistant property of the proposed SC PUF standard cell. With the help of SC PUF standard cell, the whole security chip can easily obtain stable keys and sensitive anti-invasive-attack ability by using digital design flow.

By sensing and changing the parasitic capacitance mismatch of chip pads, bumps or bonding wires, package substrate and balls, and printed circuit board (PCB) solder joints and traces into on-chip keys, the proposed chip-PCB hybrid switched-capacitor (SC) physical unclonable function (PUF) can detect the capacitance alteration caused by damaging of the package or removing of the chip from the original PCB, thereby achieving the anti-desoldering and depackaging-attack protection for the security chip. Moreover, the IO ports used for connecting the PCB traces can be shared with other normal communication function blocks, which can realize full use of IO resources while not increasing the package cost. The proposed chip-PCB hybrid SC PUF is verified in security chips by using different processes, including the traditional 28-nm CMOS process and the advanced 14- and 7-nm FinFET CMOS processes. The change of chip-PCB hybrid SC PUF’s output key when the bump of the chip is removed, or the chip is desoldered from the original PCB verifies the anti-desoldering and depackaging-attack properties of the proposed chip-PCB hybrid SC PUF. With the help of chip-PCB hybrid SC PUF, the comprehensive protection of the overall hardware environment for both the chip and the PCB hardware systems can be realized.