The major motivation behind transistor scaling is the requirement for high-speed transistors with lower fabrication costs. When the fin thickness or breadth is smaller than 10 nm in a trigate FET, charges travel in a nonconfined fashion, resulting in the creation of energy subbands and causing volume inversion. In comparison to the carrier near a surface inversion layer, volume inversion experiences less interface scattering. In large-scale integrations, we have focused on developing a 3D model for surface potential by establishing the three-dimensional Poison’s equation and building a unique fin field-effect transistor (FinFET) structure. In this context, there is a growing interest in developing a low-cost, simple solution that combines plastic (polymer) as a substrate and organic materials to create electronics such as monitors and sensors. The research examines characteristics such as silicon width, oxide thickness, doping concentration, metal work-function about gate, and various surface potentials. For different circuit configurations, it also examines the DC and AC characteristics of the FinFET structure. A differential amplifier is built for RF application based on the device specifications. This work is aimed at improving the semiconductor design structure by adjusting device parameters, analyzing the results, establishing the best FinFET device preferences, and selecting an application for the optimized device. The 3D Poisson’s equation may be used to create an analytical model of a trigate nanosize FinFET, which can then be tested using a TCAD simulator. By constructing such a FinFET, we can structure and analyze various electrostatic parameters. To facilitate the creation of FinFET-based circuits, including product development, a novel transistor needs a creative device basis. The infrastructure’s support denotes a computationally advantageous numerical model that accurately depicts a FinFET. The work presents a compact model for semiconductor manufacturing that permits separate IC productions while achieving higher levels of excellence and using less power. The design outperforms the CMOS by 22.7% in gain, 31.48% in power consumption, and 12.72% in CMRR, while operating at a 5 GHz unity gain frequency.

The Hyperbolic Frequency Modulated (HFM) and Nonlinear Frequency Modulated (NLFM) signals have been gradually used in new radar systems. These signals excitation when combined with pulse compression provides an increase in SNR at the receiver. These signals are of longer duration as compared to pulse signals of same bandwidth. Separation of echoes becomes impossible in some practical situations when these signals are used for transmission. In this paper a new method is explored to separate the time overlapping HFM and NLFM signals using the fractional fourier transform. The motivation behind using this method is because some of the techniques like time windowing and frequency domain filtering are unable to separate these signals overlapping in time and spectra. Simulation results show that using FrFT desirable outputs are obtained.

In the present scenario like COVID-19 pandemic, to maintain physical distance, the gait-based biometric is a must. Human gait identification is a very difficult process, but it is a suitable distance biometric that also gives good results at low resolution conditions even with face features that are not clear. This study describes the construction of a smart carpet that measures ground response force (GRF) and spatio-temporal gait parameters (STGP) using a polymer optical fiber sensor (POFS). The suggested carpet contains two light detection units for acquiring signals. Each unit obtains response from 10 nearby sensors. There are 20 intensity deviation sensors on a fiber. Light-emitting diodes (LED) are triggered successively, using the multiplexing approach that is being employed. Multiplexing is dependent on coupling among the LED and POFS sections. Results of walking experiments performed on the smart carpet suggested that certain parameters, including step length, stride length, cadence, and stance time, might be used to estimate the GRF and STGP. The results enable the detection of gait, including the swing phase, stance, stance length, and double supporting periods. The suggested carpet is dependable, reasonably priced equipment for gait acquisition in a variety of applications. Using the sensor data, gait recognition is performed using genetic algorithm (GA) and particle swarm optimization (PSO) technique. GA- and PSO-based gait template analyses are performed to extract the features with respect to the gait signals obtained from polymer optical gait sensors (POGS). The techniques used for classification of the obtained signals are random forest (RF) and support vector machine (SVM). The accuracy, sensitivity, and specificity results are obtained using SVM classifier and RF classifier. The results obtained using both classifiers are compared.

This research addresses the challenges of high Peak-to-Average Power Ratio (PAPR), sideband leakage, and spectrum efficiency in 5G wireless networks. We compare Universal Filtered Multi-Carrier (UFMC), Scrambled UFMC (S-UFMC), and Orthogonal Frequency Division Multiplexing (OFDM) techniques using Amplitude Phase Shift Keying (APSK) modulation. Our findings show that APSK modulation significantly reduces PAPR compared to traditional methods. Integrating Particle Swarm Optimization (PSO) with Partial Transmit Sequences (PTS)-OFDM and S-UFMC minimizes PAPR and computational complexity. Results demonstrate that S-UFMC with PSO optimization achieves superior performance, offering lower PAPR, reduced complexity, and enhanced spectral efficiency, positioning it as a promising 5G waveform. This research highlights the potential of advanced waveform designs to improve 5G communication systems. UFMC demonstrated improved spectral efficiency with sidelobe levels reaching as low as 0.2, indicating efficient spectrum utilization. The research achieved a PAPR of 7.393 dB for 16-APSK with 512 subcarriers and 7.414 dB for 1024 subcarriers after optimization. The PSO algorithm significantly reduced PAPR values, with the Scrambled UFMC system outperforming PTS-OFDM and standard UFMC in terms of PAPR.

In the rapidly advancing landscape of semiconductor technology, Gate-All-Around FET (GAA FET) stands as a promising innovation poised to redefine the capabilities of next-generation electronic devices. This paper investigates the integration challenges and potential opportunities associated with the widespread adoption of GAA FET technology. Beginning with an overview of traditional transistor limitations, we delve into the fundamentals of GAA FET structures, emphasizing their operational advantages. The analysis highlights critical integration hurdles, encompassing fabrication complexities, scalability issues, material compatibility constraints, and manufacturing intricacies. Furthermore, this paper explores innovative strategies and solutions aimed at addressing these challenges, offering insights into the transformative impact of successful GAA FET integration on the performance, efficiency, and applications of future electronic devices. Ultimately, this study underscores the significance of resolving integration obstacles to unlock the full potential of GAA FETs in driving the evolution of electronic devices.