Massive multi-core processing has recently attracted significant attention from the research community as one of the feasible solutions to satisfy constantly growing performance demands. However, this evolution path is nowadays hampered by the complexity and limited scalability of bus-oriented intra-chip communications infrastructure. The latest advantages of terahertz (THz) band wireless communications providing extraordinary capacity at the air interface offer a promising alternative to conventional wired solutions for intra-chip communications. Still, to invest resources in this field manufacturers need a clear vision of what are the performance and scalability gains of wireless intra-chip communications. Using the comprehensive hybrid methodology combining THz ray-tracing, direct CPU traffic measurements, and cycle-accurate CPU simulations, we perform the scalability study of x86 CPU design that is backward compatible with the current x86 architecture. We show that preserving the current cache coherence protocols mapped into the star wireless communications topology that allows for tight centralized medium access control a few hundreds of active cores can be efficiently supported without any notable changes in the x86 CPU logic. This important outcome allows for incremental development, where THz-assisted x86 CPU with a few dozens of cores can serve as an intermediate solution, while the truly massive multi-core system with broadcast-enabled medium access and enhanced cache coherence protocols can be an ultimate goal.

The general-purpose networks-on-chip (GP-NoC) has recently attracted the attention of the research and industry as a way to support the growing demands of computing systems. The design and the development of the communications and networking functions for such a large-scale versatile systems require knowledge of the traffic exchanged between the computing nodes. The object of the study in this paper is the last-level shared cache interface that is likely to be a traffic bottleneck in future GP-NoC architectures. First, using the direct measurements, we report on the stochastic traffic properties at large-scales, provide first two moments and distribution functions. Complementing measurements with fine-grained cycle-accurate CPU simulations, we then analyze the small-scale traffic behavior. We show that even for the simplest applications such as reading or writing of data, the nature of the traffic is stochastic, depends on the number of active cores, and irrespective of the application type, has an explicit batch structure. We further reveal that the batch sizes and inter-batch intervals can be well approximated by geometric distribution and the approximation becomes better when the number of active cores increases. These properties identify a simple arrival model that can be used in the analytical or simulation-based performance evaluation studies of the shared interface technologies in prospective NoCs.

The need of rapid design space exploration, early prototype construction and high level of reuse of technical decisions about microarchitecture in hardware design field actualize development of technologies based on custom user-specified hardware generation. However, existing approaches and tools typically offer configurability at the level of predefined set of parameters. In the article, the concept of framework architecture based on Micro-Language IP (MLIP) cores is presented. This approach facilitates creation of lightweight hardware description languages adapted to specific microarchitectural patterns. Furthermore, prototype implementation of the framework is described, followed by description of two experimental MLIP cores, rtl and pipe. These cores provide domain-specific languages for procedural generation of general-purpose RTL and pipelined hardware structures respectively. The developed means have been utilized for rapid designing of educational CPU core that has proved its operational capability in FPGA. We envision complementation of procedural hardware generation approach with microarchitecture-specific DSLs to be promising for raising the level of abstraction in microarchitecture design. This can reduce design duration of complex hardware units by up to two times, assuming either usage of common microarchitectural patterns or embodying of original ones in the new MLIP cores as an integral part of hardware design process.

In the article, the original method of embedded functional monitoring for industrial controllers is proposed. The method can be used during commissioning and operation of industrial automation systems. The method is effective for long-term monitoring in runtime and is characterized by low requirements for embedded memory. The method is based on fixation of controller's behavior in terms of state machine formal model. Observation is realized by monitoring modules embedded in industrial controllers. The results can be used as input data for existing formal verification methods.

In typical computer system design flows, hardware microarchitecture is commonly considered a dynamically developing domain, where abstract mechanisms remain mostly in conceptual form and exhibit poor source code reuse in designs. However, many important basic mechanisms appear to be pervasive and persistent. This paper summarizes original efforts to propose generic implementations of microarchitectural mechanisms for in-order and out-of-order microarchitectures and various demo designs based on these implementations. The basic EDA components proposed for this design approach are “Kernel IP (KIP) cores”—open-source collection of programmable hardware generators inferred from microarchitectural templates. KIP cores feasibility for their role is demonstrated from the viewpoints of abstract representation of microarchitectural mechanisms, support of functional differentiation of designs, and generic optimizations. Experimental designing according to this approach has shown useful separation of concerns in hardware design activities, lower design effort, and increased formalization and code reuse.