Licensed assisted access (LAA) enables the coexistence of LTE and Wi-Fi in unlicensed bands, while potentially offering improved coverage and data rates. However, cooperation with the conventional random-access protocols that employ listen-before-talk (LBT) considerations makes meeting the LTE performance requirements difficult, since delay and throughput guarantees should be delivered. In this paper, we propose a novel channel sharing mechanism for the LAA system that is capable of simultaneously providing the fairness of resource allocation across the competing LTE and Wi-Fi sessions as well as satisfying the quality-of-service (QoS) guarantees of the LTE sessions in terms of their upper delay bound and throughput. Our proposal is based on two key mechanisms: (i) LAA connection admission control (CAC) for the LTE sessions and (ii) adaptive duty cycle resource division. The only external information necessary for its operation is the current number of active Wi-Fi sessions inferred by monitoring the shared channel. In the proposed scheme, LAA-enabled LTE base station fully controls the shared environment by dynamically adjusting the time allocations for both Wi-Fi and LTE technologies, while only admitting those LTE connections that should not interfere with Wi-Fi more than another Wi-Fi access point operating on the same channel would. To characterize the key performance trade-offs pertaining to the proposed operation, we develop a new analytical model. We then comprehensively investigate the performance of the developed channel sharing mechanism by confirming that it allows to achieve a high degree of fairness between the LTE and Wi-Fi connections as well as provides guarantees in terms of upper delay bound and throughput for the admitted LTE sessions. We also demonstrate that our scheme outperforms a typical LBTbased LAA implementation.

Massive multi-core processing has recently attracted significant attention from the research community as one of the feasible solutions to satisfy constantly growing performance demands. However, this evolution path is nowadays hampered by the complexity and limited scalability of bus-oriented intra-chip communications infrastructure. The latest advantages of terahertz (THz) band wireless communications providing extraordinary capacity at the air interface offer a promising alternative to conventional wired solutions for intra-chip communications. Still, to invest resources in this field manufacturers need a clear vision of what are the performance and scalability gains of wireless intra-chip communications. Using the comprehensive hybrid methodology combining THz ray-tracing, direct CPU traffic measurements, and cycle-accurate CPU simulations, we perform the scalability study of x86 CPU design that is backward compatible with the current x86 architecture. We show that preserving the current cache coherence protocols mapped into the star wireless communications topology that allows for tight centralized medium access control a few hundreds of active cores can be efficiently supported without any notable changes in the x86 CPU logic. This important outcome allows for incremental development, where THz-assisted x86 CPU with a few dozens of cores can serve as an intermediate solution, while the truly massive multi-core system with broadcast-enabled medium access and enhanced cache coherence protocols can be an ultimate goal.

Dynamic blockage of radio propagation paths between the user equipment (UE) and the 5G New Radio (NR) Base Station (BS) induces abrupt rate fluctuations that may lead to sub-optimal performance of the Transmission Control Protocol (TCP) protocol. In this work, we characterize the effects of dynamic human blockage on TCP throughput at the 5G NR air interface. To this aim, we develop an analytical model that expresses the TCP throughput as a function of the round-trip time (RTT), environmental, and radio system parameters. Our results indicate that the blockage affects TCP throughput only when the RTT is comparable to the blocked and non-blocked state durations when the frequency of state changes is high. However, such conditions are not typical for dynamic body blockage environments allowing TCP to benefit from the high bandwidth of 5G NR systems fully.

Stochastic geometry has recently gained popularity for performance assessment of wireless networks. The application of this approach is conditioned on the availability of closedform expressions for probability distributions of the distance between the receiver and interfering nodes. These expressions are available for the simple point processes, e.g., the Poisson point process, and area geometries only. The motivation of this letter is to draw the attention of the wireless research community to a new methodology for estimating interference in spatially random networks. We show that using the integral geometry and working with interference sets rather than interference distances one can approximate the interference for any convex deployment areas and general distribution of interfering nodes.

The general-purpose networks-on-chip (GP-NoC) has recently attracted the attention of the research and industry as a way to support the growing demands of computing systems. The design and the development of the communications and networking functions for such a large-scale versatile systems require knowledge of the traffic exchanged between the computing nodes. The object of the study in this paper is the last-level shared cache interface that is likely to be a traffic bottleneck in future GP-NoC architectures. First, using the direct measurements, we report on the stochastic traffic properties at large-scales, provide first two moments and distribution functions. Complementing measurements with fine-grained cycle-accurate CPU simulations, we then analyze the small-scale traffic behavior. We show that even for the simplest applications such as reading or writing of data, the nature of the traffic is stochastic, depends on the number of active cores, and irrespective of the application type, has an explicit batch structure. We further reveal that the batch sizes and inter-batch intervals can be well approximated by geometric distribution and the approximation becomes better when the number of active cores increases. These properties identify a simple arrival model that can be used in the analytical or simulation-based performance evaluation studies of the shared interface technologies in prospective NoCs.