We report the fabrication and characterization of A2RAM capacitorless memory cell on silicon-on-insulator (SOI). Holes and electrons are separated in two superposed p- and n-channel regions. The retrograde p-n doping in a 36-nm-thick body has been successfully tailored by epitaxial regrowth, without any alteration of the CMOS/SOI process. We document the detailed device operation and its attractive performance in terms of current margin, retention time, and variability.

The Z²-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z²-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.

Supercoupling effect prevents the simultaneous formation of inversion and accumulation channels at the two interfaces of ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistor. Our work highlights that short-channel effects enhance supercoupling and turn it into a two-dimensional mechanism. The lateral influence of source and drain terminals is evidenced with experimental data and examined by 2D numerical simulations which reveal the roles of gate length and drain bias. The critical Si-film thickness, below which supercoupling arises, is significantly increased in short-channel transistors. The impact of back-gate and drain bias, BOX thickness, and quantum effects is documented and practical applications are discussed.