The recently reported large enhancement of the electron mobility in strained-Si inversion layers at large carrier concentrations cannot be easily explained: The strong carrier confinement in inversion layers removes the sixfold degeneracy of the conduction-band minima, much as tensile in-plane strain does, so that the effect of strain should become irrelevant at large sheet carrier densities. The problem is studied by calculating the electron mobility accounting for scattering with phonons and interface roughness. Surprisingly, the latter process is found to be significantly stronger in strained layers for a given interface roughness. Only the ad hoc assumption of increasingly smoother interfaces with increasing strain seems to explain the data.

The electron mobility in a double-gate silicon-on-insulator (DGSOI) device is studied as a function of the transverse effective field and silicon layer thickness. The contributions of the main scattering mechanisms (phonon scattering, surface roughness scattering due to both ${\mathrm{Si–SiO}}_{\mathrm{2}}$ interfaces, and Coulomb interaction with the interface traps of both interfaces) are taken into account and carefully analyzed. We demonstrate that the contribution of surface scattering mechanisms is by no means negligible; on the contrary, it plays a very important role which must be taken into account when calculating the mobility in these structures. The electron mobility in DGSOI devices as $T_w$ decreases is compared with the mobility in single-gate silicon-on-insulator structures (i) when only phonon scattering is considered, (ii) when the effect of surface-roughness scattering is taken into account, and (iii) when the contribution of Coulomb interaction with charges trapped at both interfaces is taken into consideration (in addition to phonon and surface roughness scattering). From this comparison we determined (in the three cases above) the existence of the following three regions: (i) A first region for thick silicon layers ${\mathrm{(T}}_w\text{>20–30\hspace{0.05em}}\mathrm{nm}\mathrm{),}$ where mobility for both structures tends to coincide, approaching the bulk value. (ii) As $T_w$ decreases we show that volume inversion modifies the electron transport properties by reducing the effect of all scattering mechanisms. Accordingly, the electron mobility in DGSOI inversion layers increases by an important factor which depends on the silicon thickness and the transverse effective field. (iii) Finally, for very small thicknesses, the limitations to electron transport are due to geometrical effects, and therefore the two mobility curves, which again coincide, fall abruptly. We show the existence of a range of thicknesses of a silicon layer (between 5 and 20 nm in which electron mobility is improved by 25% or more.

We show by simulation that electron mobility and velocity overshoot are greater when strained inversion layers are grown on SiGe-On-insulator substrates (strained Si/SiGe-OI) than when unstrained silicon-on-insulator (SOI) devices are employed. In addition, mobility in these strained inversion layers is only slightly degraded compared with strained bulk Si/SiGe inversion layers, due to the phonon scattering increase produced by greater carrier confinement. Poisson and Schroedinger equations are self-consistently solved to evaluate the carrier distribution in this structure. A Monte Carlo simulator is used to solve the Boltzmann transport equation. Electron mobility in these devices is compared to that in SOI inversion layers and in bulk Si/SiGe inversion layers. The effect of the germanium mole fraction x, the strained-silicon layer thickness, TSi, and the total width of semiconductor (Si+SiGe) slab sandwiched between the two oxide layers, Tw were carefully analyzed. We observed strong dependence of the electron mobility on TSi, due to the increase in the phonon scattering rate as the silicon layer thickness is reduced, a consequence of the greater confinement of the carriers. This effect is less important as the germanium mole fraction, x, is reduced, and as the value of TSi increases. For TSi>20 nm, mobility does not depend on TSi, and maximum mobility values are obtained.

The effect of surface roughness scattering on electron transport properties in extremely thin silicon-on-insulator inversion layers is carefully analyzed. It is shown that if the silicon layer is thin enough (thinner than 10 nm) the presence of the buried interface plays a very important role, both by modifying the surface roughness scattering rate due to the gate interface, and by itself providing a non-negligible scattering rate. The usual surface roughness scattering model in bulk silicon inversion layers is shown to overestimate the effect of the surface-roughness scattering due to the gate interface as a consequence of the minimal thickness of the silicon layer. In order to account for this effect, an improved model is provided. The proposed model allows the evaluation of the surface roughness scattering rate due to both the gate interface and the buried interface. Once the scattering rates are evaluated, electron mobility is calculated by the Monte Carlo method. The effect of the buried interface roughness on electron mobility is carefully analyzed by changing the height of the roughness. The effect of the silicon layer thickness on this scattering mechanism is also considered.

A physical model for trap-assisted inelastic tunnel current through potential barriers in semiconductor structures has been developed. The model is based on the theory of multiphonon transitions between detrapped and trapped states and the only fitting parameters are those of the traps (energy level and concentration) and the Huang–Rhys factor. Therefore, dependences of the trapping and detrapping processes on the bias, position, and temperature can be obtained with this model. The results of the model are compared with experimental data of stress induced leakage current in metal-oxide-semiconductor devices. The average energy loss has been obtained and an interpretation is given of the curves of average energy loss versus oxide voltage. This allows us to identify the entrance of the assisted tunnel current in the Fowler–Nordheim regime. In addition, the dependence of the tunnel current and average energy loss on the model parameters has been studied.