A high power density is required in wide band gap power semiconductor packaging, which has led to the popularity of sintered nanosilver as an interconnecting material. However, affected by stochastically distributed voids in its microstructure, this material in practice exhibits instability leading to reduced reliability. In this paper, a computational multiscale modeling method is proposed to simulate the influence of micro-voids on macro-properties, providing an efficient tool to analyze the aforementioned problem. At the micro-scale, the three-parameter Weibull distribution of the equivalent Young’s modulus and the normal distribution of the equivalent Poisson’s ratio are captured by Monte Carlo-based finite element simulation on the reconstructed stochastic representative elements, where the density and distribution morphology of micro-voids are taken into consideration. At the macro-scale, the effect of the microscopic voids is transferred through a random sampling process to construct the multiscale model. The effectiveness and validity of the proposed method are verified through experimental case studies involving the modeling of nanosilver-sintered joints sintered at temperatures of 275°C and 300°C. In addition, the effects of the sintering temperature on the dispersion of the micro-voids, the distribution fluctuation of the constitutive parameters, and the mechanical properties are also discussed based on numerical and experimental results. Graphical

Traditional lithium-ion battery (LiB) modeling does not provide sufficient information to accurately verify battery performance under real-time dynamic operating conditions, particularly when considering various aging modes and mechanisms. This paper proposes a lithium-ion battery digital twin that can capture real-time data and integrate the strong coupling between SEI layer growth, anode crack propagation, drying up of Electrolytes, and lithium plating. It can be utilized to predict the degradation behavior, voltage-current profiles in dynamic aging conditions, and analyze the lithium inventory loss (LLI) of Nickel-Manganese-Cobalt-Oxide (NMC) lithium-ion batteries. Commercially available 18650 cylindrical NMC Samsung battery cells were investigated. The cathode and anode materials are LiNi0.5Co0.2Mn0.3O2 and synthetic graphite, respectively. Four dynamic aging test cases using 1C, 1.3C, MC (multistep charging), and 2C, were designed and performed at 25 °C. The reference performance test (RPT) was repeated every 100 full equivalent cycles (FECs) until the cells reached 20 % capacity fade. Figure 1 shows the real-time voltage and current profile captured and predicted by the digital twin. The model takes into account LLI induced by SEI growth and lithium plating, aligning with the LLI calibrated from the differential voltage (DV) endpoint shift (Figure 1h). Based on the model results, SEI growth is found to be the primary contributor to capacity loss before 500 FECs. SEI-induced degradation is minimal under the MC protocol, with the capacity loss varying by less than 5.22% across four test cases (Figure 1e). After 500 FECs, anode cracking becomes a non-linear accelerated aging factor. The crack propagation stabilizes in the initial 200 FECs, followed by unstable accelerated growth leading to capacity loss. Subsequently, a rapid acceleration in capacity loss occurs after 700 FECs (Figure 1f). The growth of anode cracks under the MC aging protocol has a much slower effect on capacity loss compared to the 2C and 1.3C before 500 FECs, as strongly confirmed by the post-mortem analysis. In addition, the lithium plating phenomenon triggers two orders of magnitude less capacity loss than SEI growth and cracking at 25 °C. The MC protocol demonstrates an effective reduction in lithium plating capacity loss compared to the other three traditional charging protocols (Figure 1g). This digital twin can represent a firm physical foundation for future physics-informed machine learning development to predict LiBs degradation behavior. Figure 1. Real-time voltage and current captured and predicted by our designed digital twin under (a) 1C-WLTC, (b)1.3C-WLTC, (c) MC-WLTC, and (d) 2C-WLTC aging profiles. Additionally, (f) illustrates capacity loss density for the four protocols attributed to (e) SEI film growth, (f) anode crack propagation, (g) Li plating, and (h) LLI prediction by the digital twin and DV measurement. Figure 1

10 kVSiC-MOSFETpowermodulesarebeingdevelopedformedium-voltageapplications, but their reliability has not yet been fully verified. This study demonstrates the power cycle test (PCT) on 10 kV SiC-MOSFET power modules with different wire bond layout designs to investigate the influence on their failure points. The 10 kV SiC-MOSFET is 8.1 mm square in size and 20 A/die. Only four source wire bonds are needed, which provides enough flexibility for the wire bond layout. The wire bonds are placed on the edge of each source pad to reduce the wire heating ∆ T _wire by 6.2% compared to the conventional central wire bond placement from the 3D simulation. These differences were verified in the PCT on ∆ T _diemax : 104−108 °C. As a result, itwas observed that samples with the modified layout, which achieved a lower ∆ T _wire , exhibited a shift in failure mode from wire lift-off to solder failure, while maintaining a similar lifetime under higher die temperatures.