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Dr. Labonnah Farzana Rahman is working as a post-Doctoral researcher in the Institute for Environment and Development at the National University of Malaysia (UKM). Dr. Labonnah received her M.Sc and a Ph.D. degree in Electrical, Electronic, and Systems Engineering from UKM, in 2012 and 2017, respectively. She has a specialization in the field of VLSI design, Analog and Digital RFIC design, RFID tag memory, Microchip design and fabrication, RFID systems. Currently, she is working on the traceability solution for the fisheries industry in Malaysia using RFID. She has published many articles with an h-index of 11.
The fishing industry is identified as a strategic sector to raise domestic protein production and supply in Malaysia. Global changes in climatic variables have impacted and continue to impact marine fish and aquaculture production, where machine learning (ML) methods are yet to be extensively used to study aquatic systems in Malaysia. ML-based algorithms could be paired with feature importance, i.e., (features that have the most predictive power) to achieve better prediction accuracy and can provide new insights on fish production. This research aims to develop an ML-based prediction of marine fish and aquaculture production. Based on the feature importance scores, we select the group of climatic variables for three different ML models: linear, gradient boosting, and random forest regression. The past 20 years (2000–2019) of climatic variables and fish production data were used to train and test the ML models. Finally, an ensemble approach named voting regression combines those three ML models. Performance matrices are generated and the results showed that the ensembled ML model obtains R2 values of 0.75, 0.81, and 0.55 for marine water, freshwater, and brackish water, respectively, which outperforms the single ML model in predicting all three types of fish production (in tons) in Malaysia.
Labonnah Farzana Rahman; Mohammad Marufuzzaman; Lubna Alam; Azizul Bari; Ussif Rashid Sumaila; Lariyah Mohd Sidek. Developing an Ensembled Machine Learning Prediction Model for Marine Fish and Aquaculture Production. Sustainability 2021, 13, 9124 .
AMA StyleLabonnah Farzana Rahman, Mohammad Marufuzzaman, Lubna Alam, Azizul Bari, Ussif Rashid Sumaila, Lariyah Mohd Sidek. Developing an Ensembled Machine Learning Prediction Model for Marine Fish and Aquaculture Production. Sustainability. 2021; 13 (16):9124.
Chicago/Turabian StyleLabonnah Farzana Rahman; Mohammad Marufuzzaman; Lubna Alam; Azizul Bari; Ussif Rashid Sumaila; Lariyah Mohd Sidek. 2021. "Developing an Ensembled Machine Learning Prediction Model for Marine Fish and Aquaculture Production." Sustainability 13, no. 16: 9124.
Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.
Labonnah Rahman; Mohammad Marufuzzaman; Lubna Alam; Mazlin Mokhtar. Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications. Electronics 2021, 10, 676 .
AMA StyleLabonnah Rahman, Mohammad Marufuzzaman, Lubna Alam, Mazlin Mokhtar. Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications. Electronics. 2021; 10 (6):676.
Chicago/Turabian StyleLabonnah Rahman; Mohammad Marufuzzaman; Lubna Alam; Mazlin Mokhtar. 2021. "Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications." Electronics 10, no. 6: 676.
A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID–EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.
Labonnah Farzana Rahman; Mohammad Marufuzzaman; Lubna Alam; Lariyah Mohd Sidek; Mamun Bin Ibne Reaz. A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM. PLOS ONE 2020, 15, e0225408 .
AMA StyleLabonnah Farzana Rahman, Mohammad Marufuzzaman, Lubna Alam, Lariyah Mohd Sidek, Mamun Bin Ibne Reaz. A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM. PLOS ONE. 2020; 15 (2):e0225408.
Chicago/Turabian StyleLabonnah Farzana Rahman; Mohammad Marufuzzaman; Lubna Alam; Lariyah Mohd Sidek; Mamun Bin Ibne Reaz. 2020. "A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM." PLOS ONE 15, no. 2: e0225408.
Labonnah F. Rahman; Mamun B. I. Reaz; Mohammad Marufuzzaman. Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM. International Journal of Computer Theory and Engineering 2015, 7, 177 -180.
AMA StyleLabonnah F. Rahman, Mamun B. I. Reaz, Mohammad Marufuzzaman. Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM. International Journal of Computer Theory and Engineering. 2015; 7 (3):177-180.
Chicago/Turabian StyleLabonnah F. Rahman; Mamun B. I. Reaz; Mohammad Marufuzzaman. 2015. "Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM." International Journal of Computer Theory and Engineering 7, no. 3: 177-180.
The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.
Labonnah Farzana Rahman; Mamun Bin Ibne Reaz; Chia Chieu Yin; Mohammad Alauddin Mohammad Ali; Mohammad Marufuzzaman. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process. PLOS ONE 2014, 9, e108634 .
AMA StyleLabonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali, Mohammad Marufuzzaman. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process. PLOS ONE. 2014; 9 (10):e108634.
Chicago/Turabian StyleLabonnah Farzana Rahman; Mamun Bin Ibne Reaz; Chia Chieu Yin; Mohammad Alauddin Mohammad Ali; Mohammad Marufuzzaman. 2014. "Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process." PLOS ONE 9, no. 10: e108634.
Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.
Labonnah Farzana Rahman; Mamun Bin Ibne Reaz; Chia Chieu Yin; Mohammad Marufuzzaman; Mohammad Anisur Rahman. A High-Speed and Low-Offset Dynamic Latch Comparator. The Scientific World Journal 2014, 2014, 1 -8.
AMA StyleLabonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Marufuzzaman, Mohammad Anisur Rahman. A High-Speed and Low-Offset Dynamic Latch Comparator. The Scientific World Journal. 2014; 2014 ():1-8.
Chicago/Turabian StyleLabonnah Farzana Rahman; Mamun Bin Ibne Reaz; Chia Chieu Yin; Mohammad Marufuzzaman; Mohammad Anisur Rahman. 2014. "A High-Speed and Low-Offset Dynamic Latch Comparator." The Scientific World Journal 2014, no. : 1-8.