The constant-current (CC) method uses a current criterion to determine the threshold voltage (V_TH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on V_DS, allowing to coherently determine V_TH for the entire range of V_DS from linear operation to saturation. The method uses commonly available I_D versus V_G data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

This paper examines the relation between the structure of a compact MOSFET model and its ability to model harmonic distortion. It is found that non-singular behavior at zero drain bias is essential for qualitatively correct simulations of the third harmonic power dependence. Specifically, nonlinear distortion analysis requires that the Gummel symmetry condition be satisfied by the compact model. A simple procedure to enforce the Gummel symmetry without increasing the complexity of the model is incorporated in an advanced surface-potential-based MOSFET model to enable correct harmonic distortion modeling.

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (L_G) and with a total overlap of the back gate over the channel region (L_G + L_IN). A potential well is created by biasing the back gate (V_BG) in accumulation, while the front gate (V_FG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.