The constant-current (CC) method uses a current criterion to determine the threshold voltage (V_TH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on V_DS, allowing to coherently determine V_TH for the entire range of V_DS from linear operation to saturation. The method uses commonly available I_D versus V_G data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Analog/RF performance of double-gate MOSFETs in the sub-20-nm regime is investigated using ATLAS device simulator. It is shown that graded channel dual material double gate (GCDMDG) achieves higher drain current, peak transconductance, and higher values of cutoff frequency at lower drain currents. This novel architecture also provides better intrinsic gain for an amplifier. A new analog/RF figure of merit, gain transconductance frequency product (GTFP) is proposed that includes both the switching speed and intrinsic gain of the device and is very useful for circuit design. The peak GTFP is observed at the higher end of moderate inversion, slightly above threshold. The GCDMDG device outperforms in terms of GTFP and is more favorable for shorter channel length devices.

An analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs with trapezoidal cross section is proposed. The compact model of rectangular FinFETs is extended to trapezoidal FinFETs using equivalent nonplanar device parameters and corner effects. The model has been validated by comparing the results with those of 3-D numerical device simulations. The very good accuracy of the drain current and transcapacitances makes the proposed model suitable for implementation in circuit simulation tools.

In this paper, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths. For the first time, approaches for excess noise factor modeling are validated versus measurements. Furthermore, important RF CMOS figures of merit are examined over many CMOS generations. With the scaling of CMOS technology, optimum RF performance is shown to be shifted from higher moderate toward lower moderate inversion, providing important guidelines for RFIC design. The results are validated with the charge-based EKV3 compact model, which considers short-channel effects such as channel length modulation, velocity saturation, and carrier heating.