This work presents the design of an ultra-low-power self-biased 400-pA current source. We propose the use of a very simple topology along with a design methodology based on the concept of inversion level. An efficient design methodology has resulted in a cell area around 0.045 mm/sup 2/ in the AMI 1.5-/spl mu/m CMOS technology and power consumption around 2 nW for 1.2-V supply. Simulated and experimental results validate the design and show that the current source can operate at supply voltages down to 1.1 V with a good regulation (<6% /V variation of the supply voltage) in a 1.5-/spl mu/m technology.

In this paper, series-parallel (SP) current-division will be employed for the design of very low transconductance OTAs. From the theory and measurements, it will be shown that SP mirrors allow the division of currents with division factors of thousands, without reducing matching or noise performance. SP mirrors will be applied to the design of OTAs ranging from 33 pS to a few nS, with up to 1 V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3-s time-constant integrator will also be presented. Several design concerns will be studied: linearity, offset, noise, and leakages, as well as layout techniques. A final comparative analysis concludes that SP association of transistors allows the design of very efficient transconductors, for demanding applications in the field of implantable electronics, among others

In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at which the hysteresis appears and to obtain a rough estimation of the hysteresis width. It is shown that the theoretical minimum supply voltage required to obtain hysteresis is 2ln(2 + √5)kT/q = 75 mV at room temperature. A test chip with CMOS Schmitt triggers was designed and fabricated in a 180 nm technology in order to study their operation at supply voltages between 50 mV and 1000 mV.

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.

In order to investigate the minimum supply voltage for MOSFET oscillators, three topologies were studied. Two of them, namely the enhanced swing inductive-load ring and the enhanced swing Colpitts oscillators, can operate with supply voltages below the thermal voltage. Simplified theoretical expressions for the minimum supply voltage of the oscillators were derived. Measurement results obtained using prototypes built with zero-VT transistors and high-quality-factor inductors confirmed the operation of one of the oscillators down to a supply voltage below 5 mV.