This paper proposes a novel image encryption and decryption scheme, called Square Block Division-Fibonacci (SBD-Fibonacci), which dynamically partitions any input image into optimally sized square blocks to enable efficient encryption without resizing or distortion. The proposed encryption scheme can dynamically adapt to the image dimensions and ensure compatibility with images of varying and high resolutions, while it serves as a yardstick for any symmetric-key image encryption algorithm. An optimization model, combined with the Lagrange Four-Square theorem, minimizes trivial block sizes, strengthening the encryption structure. Encryption keys are generated using the direct sum of generalized Fibonacci matrices, ensuring key matrix invertibility and strong diffusion properties and security levels. Experimental results on widely-used benchmark images and a comparative analysis against State-of-the-Art encryption algorithms demonstrate that SBD-Fibonacci achieves high entropy, strong resistance to differential and statistical attacks, and efficient runtime performance—even for large images.

Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global placement generates an optimized instance of the design targeting a set of metrics, while ignoring rules pertaining its feasibility. Legalization and detailed placement rectify this situation, attempting to attain minimum quality loss by often disregarding the connectivity between cells and making runtime the focal point of these steps. In this article, we present a set of variations on a connectivity-based legalization scheme that can either be applied as a legalizer or a detailed placer. The variations can be applied in the entirety of the chip area or in the confinement of a user-specified bin while they are guided by various optimization goals, e.g., total wire length, displacement and density. We analytically describe our variations and evaluate them through extensive simulations on commonly used benchmarks.

The transition to a globalized, fabless semiconductor manufacturing model has integrated third-party foundries and external intellectual property (IP) vendors into the integrated circuit (IC) design cycle. While this collaborative system promotes innovation, it also exposes layouts to security threats. Protecting these designs is paramount; however, applying traditional encryption methodologies fundamentally alters the syntactic hierarchy of the industry-standard GDSII stream format, causing electronic design automation (EDA) tools to crash. Furthermore, a full encryption hinders modern system-on-chip (SoC) development, where different teams require access to specific modules of the design, without exposing the entire IP. To resolve this issue between collaborative layout sharing and zero-trust security, this paper presents a software implementing an encryption engine. By applying the NIST-standardized FF1 Format-Preserving Encryption (FPE) algorithm directly to the geometric data, the proposed software obfuscates sensitive spatial coordinates and structural nomenclature while maintaining the native GDSII format. The engine embeds multi-tiered cryptographic access control directly into the layout, utilizing native metadata properties. This framework allows proprietary logic to be securely compartmentalized, ensuring that interacting parties only view the specific structures they possess the clearance to decrypt.