The registration of synthetic aperture radar (SAR) and optical images is critical in multimodal remote sensing image fusion. In recent years, deep learning-based registration networks have been continuously introduced. However, owing to the significant disparities in viewing angles and radiometric properties between SAR and optical images, current deep learning methods struggle to fully exploit the physical properties of radar imaging. Additionally, many existing matching networks typically perform only a forward pass, resulting in suboptimal model performance. This paper proposes a cyclic iterative registration SAR mechanism network (termed as CIRSM-Net) for the registration of SAR and optical images. Firstly, we design a learning module that integrates the radar equation with a microwave scattering model to capture deep features from SAR images, and design a corresponding scattering feature loss to aid in better generalization across various radar images. Then, to explore optimization methods for matching networks, this study proposes a strategy of multiple iterative optimizations within the matching network. Specifically, it integrates speeding-up radiation-variation insensitive feature transform (RIFT2) supervision in the backend matching network and iteratively optimizes the final output. Finally, during the iteration process, we propose an innovative matching loss function that combines the rotation invariance supervision of RIFT2 with iterative optimization techniques to enhance feature matching accuracy. Experimental results on both public and our own datasets additionally confirm the effectiveness and superiority of the proposed approach, demonstrating its significant potential for practical applications.

With the application of object detection (OD) technology in various fields, common OD methods have been increasingly widely used, which poses a challenge to their calculative performance and accuracy. To improve the computational performance of OD algorithms, a general-purpose accelerated coprocessor was designed and implemented based on the extensibility of the RISC-V architecture. The accelerator was transformed into the form of a coprocessor and connected to its CPU core through the EAI coprocessor interface. Meanwhile, the corresponding instructions were designed, and the acceleration library functions were established. Finally, the performance and resource depletion of the coprocessor were analyzed on the FPGA platform. The experimental results suggest that only 10,091 LUTs were consumed by the accelerated coprocessor designed in this study, accounting for 52.2% of the entire SoC system. Moreover, the processing capacity of the YOLOv3 algorithm was 6.33 times that of a general-purpose CPU.