Phase change materials allow non-volatile, fast-speed storage-class memory. However, thermal stability and reliability are the key challenges that limit their extensive applications, especially high-temperature applications. Here, we demonstrate an alloying strategy through alloying Ta into Ge₂Sb₂Te₅ (GST), which presents robust data retention at 167 °C for 10 years, power consumption as low as one order of magnitude, and ten times longer endurance as compared with a GST-based device. The mechanism of the microstructure evolution of Ta alloying is clarified by using advanced electron microscopy and a theoretical method. The formation of strong Ta–Te coordinate bonds increases the rigidity of amorphous atomic matrices. In the grain, partial Ta is separated at the grain boundary, and inner-grain Ta atoms immensely increase cationic migration energy barriers to stabilize the metastable cubic phase. Subsequently, the inner-grain Ta atoms slowly aggregate at the grain boundary under the action of an electric field. Thus, grain growth and elemental segregation are further inhibited, effectively improving the reliability of the device. The superior thermal stability and reliability of Ta-GST devices pave the way for their widespread applications in automotive electronics and aerospace.

Non-volatile memories (NVMs) outperform traditional SRAMs in terms of low power consumption, high capacity, near-zero power-on delay, and high error-resistance. Researchers have demonstrated the possibilities of implementing FPGA building blocks with various types of NVMs. However, NVMs also bring several new design challenges to FPGAs: the slow write performance of NVM may degrade FPGA (re)configuration speed, while the limited write endurance of NVM constrains the number of times that the FPGA can be (re)configured. Unfortunately, none of these NVM features are taken into consideration in current FPGA synthesis tools, which have been optimized solely for SRAM-based FPGAs. To tackle this limitation, we propose to make the FPGA placement process aware of the slow and costly NVM writes. Our contributions are three-fold: We first construct mathematical models to characterize reconfiguration costs in NVM-based FPGAs. Second, we identify three types of flexibilities that can be exploited to reduce the reconfiguration cost. Finally, we present three approaches for designers to fine-tune the placement process to balance the reconfiguration cost and traditional timing and routability constraints according to their needs. The proposed algorithms are incorporated in Verilog-to-Routing (VTR) CAD tool. Experiments on standard MCNC benchmark circuits show that our approach eliminates up to 67% NVM writes during the reconfiguration process, thus effectively improving the performance and endurance of NVM-based FPGAs.

Phase change memory (PCM), due to the advantages in capacity and endurance, has the opportunity to become the next generation of general−purpose memory. However, operation speed and data retention are still bottlenecks for PCM development. The most direct way to solve this problem is to find a material with high speed and good thermal stability. In this paper, platinum doping is proposed to improve performance. The 10-year data retention temperature of the doped material is up to 104 °C; the device achieves an operation speed of 6 ns and more than 3 × 10⁵ operation cycles. An excellent performance was derived from the reduced grain size (10 nm) and the smaller density change rate (4.76%), which are less than those of Ge₂Sb₂Te₅ (GST) and Sb₂Te₃. Hence, platinum doping is an effective approach to improve the performance of PCM and provide both good thermal stability and high operation speed.

In this article, we present a RSD (Rectangle defined by ‘Source’ node and ‘Destination’ node) fault block model for highly efficient fault-tolerant Manhattan routing algorithms in 2D mesh. For any given pair of the source node and the destination node, RSD fault block model will not take the shape of a single RSD faulty block and fault nodes outside RSD into account. The procedure of constructing of all RSD fault blocks is restricted in the range of RSD and no available Manhattan paths will be omitted. The worst-case and average time complexity of constructing RSD fault blocks are O( <mml:math><mml:msubsup><mml:mrow><mml:mi mathvariant="bold-italic">M</mml:mi></mml:mrow><mml:mrow><mml:mn mathvariant="bold">0</mml:mn></mml:mrow><mml:mrow><mml:mn mathvariant="bold">2</mml:mn></mml:mrow></mml:msubsup></mml:math>M02 + N²) and O( <mml:math><mml:msubsup><mml:mrow><mml:mi mathvariant="bold-italic">M</mml:mi></mml:mrow><mml:mrow><mml:mn mathvariant="bold">0</mml:mn></mml:mrow><mml:mrow><mml:mn mathvariant="bold">2</mml:mn></mml:mrow></mml:msubsup></mml:math>M02 ) (N is not the length and width of the whole 2D mesh but that of RSD, M₀ is the number of initial fault nodes not in the whole 2D mesh but in RSD), respectively. Using the result of constructing RSD fault block, it is easy to judge whether there exist some Manhattan paths or not. Then all possible fault-tolerant Manhattan paths achieved can provide flexibility of designing different fault-tolerant Manhattan routing algorithms with or without some restrictions. It is more efficient for fault-tolerant multicast Manhattan routing algorithms.