Phase change materials allow non-volatile, fast-speed storage-class memory. However, thermal stability and reliability are the key challenges that limit their extensive applications, especially high-temperature applications. Here, we demonstrate an alloying strategy through alloying Ta into Ge₂Sb₂Te₅ (GST), which presents robust data retention at 167 °C for 10 years, power consumption as low as one order of magnitude, and ten times longer endurance as compared with a GST-based device. The mechanism of the microstructure evolution of Ta alloying is clarified by using advanced electron microscopy and a theoretical method. The formation of strong Ta–Te coordinate bonds increases the rigidity of amorphous atomic matrices. In the grain, partial Ta is separated at the grain boundary, and inner-grain Ta atoms immensely increase cationic migration energy barriers to stabilize the metastable cubic phase. Subsequently, the inner-grain Ta atoms slowly aggregate at the grain boundary under the action of an electric field. Thus, grain growth and elemental segregation are further inhibited, effectively improving the reliability of the device. The superior thermal stability and reliability of Ta-GST devices pave the way for their widespread applications in automotive electronics and aerospace.

A novel selector exhibits a high drive current of 10 mA by combining high-mobility Ag with highly defective GeTe₈.

Multilevel-cell (MLC) phase change memory (PCM) usually evaluated in the program method, delay or write energy while the endurance characteristic has not been focused on. In this paper, we exploit a staircase-up program and verify method in the current-driven 4 Mb PCM chip to achieve MLC storage. The direct results of the change in the R – I characteristic and resistance distribution during the cycles are displayed. According to the measurement, the PCM device shows four separable resistance levels after 10 ⁶ operation cycles with a decreasing resistance of full-crystalline state. And the resistance drift and read disturb which affect the cell reliability also are briefly tested. The MLC device shows a good performance where four resistance levels can be separated well after 1000 s and the read endurance under 0.3 V is retained up to 10 ⁹ cycles.

Phase change memory (PCM) device using a diode as selector exhibits a high level of integration based on 40 nm process, but it still has some reliability problems, such as read disturbance and writing performance. In this paper, we test and improve the read/write reliability of one diode and one resistor (1D1R) structure cell in array with cell size of 12 F ² (0.16 μ m × 0.12 μ m). The 1D1R device has good performance with ultra-high speed (20 ns) and low programming voltage (3.3 V). The cell programmed by current pulse has a better performance than that of voltage operation in amorphous state with respect to read disturb immunity. The ratio of reset/set resistance can be improved by choosing appropriate parameter of write operation. In addition, the endurance characteristics of the devices are investigated. The optimization in read/write operation guarantee that 1D1R device can satisfy the requirements for the high-speed and high-density applications.