A novel lateral double-diffused MOSFET with multi-ring substrate (M-R LDMOS) is proposed. New high electric field peaks are introduced by the M-R due to the effect of the electric field modulation, which makes the lateral and vertical electric field distributions more uniform at the same time. As a consequence, the breakdown voltage (BV) of M-R LDMOS is enhanced significantly. The simulation result shows that the BV of M-R LDMOS is 566 V with the drift region length of $30~\mu \text{m}$ . Furthermore, the figure-of-merit of M-R LDMOS is 3.05 MW/cm ² , increased by 190%, 45%, and 24.5% in comparison with the conventional LDMOS, the step doping drift LDMOS, and the assisted deplete-substrate layer LDMOS, respectively. M-R LDMOS has a much better performance. In addition, the proposed M-R LDMOS uses the highly doped substrate ( $3\times 10^{15}$ cm ⁻³ ), which significantly reduces the cost of substrate.

A novel superjunction (SJ) vertical UMOSFET with semi-insulating POly-crystalline silicon pillar (SIPOS SJ-UMOS) is proposed and its mechanism is investigated by TCAD simulations. In the off-state, the reshape effect of SIPOS pillars enhances the vertical electric field strength and weakens the lateral field component, which increases the breakdown voltage (BV). In addition, the highly doped N-pillars are allowed for the proposed device due to the enhanced depletion by the SIPOS pillars, which leads to a low specific ON resistance (R _ON,sp ). In the on-state, an accumulation layer is formed in drift region leading to an additional reduction in the R _ON,sp . Simulation results show that the RON,sp decreases 59%, and BV increases by 16.7%, simultaneously, breaking the SJ silicon limit, compared with those of a conventional SJ-UMOS with the same drift length. Moreover, the charge-imbalance endurance of SIPOS SJ-UMOS is also improved.

A new theory of lateral double-diffused MOS (LDMOS) by the folded-silicon substrate field-effect (FSLDMOS) with the complete 3-D REduced SURface Field (RESURF) is proposed in this paper for the first time. The analytical model for the relationship between the breakdown voltage (BV) and the specific ON-resistance (R _ON,sp ) of FSLDMOS is obtained, which breaks the limit relationship of the superjunction (SJ) LDMOS by applying three kinds of methods, including the additional electric-field modulation effect, majority carrier accumulation, and increasing the effective conduction paths simultaneously. In the analytical model, the influence of the structural parameters of the folded-drift and electric field modulation coefficients is considered. Besides, the optimal doping concentration of the folded-drift region for FSLDMOS is derived, which can give guidance for the dose of the folded-drift region. The results indicate that a new analytical expression for the relationship between the BV and R _ON,sp is obtained, which breaks the limit relationship of the SJ LDMOS by the complete 3-D RESURF. All analytical results are well verified by the simulation results conducted by ISE-TCAD, showing the validity of the presented model.

A novel 700 V triple REduced SURface Field (RESURF) lateral double-diffused MOSFETs (LDMOS) with a variable high- K (VHK) dielectric trench for smart power applications is proposed and studied by TCAD simulations. Compared with conventional triple RESURF (CTR) LDMOS, the new structure features a composite high- K (HK) dielectric trench embedded in the drain edge. First, a higher HK dielectric layer is in the upper trench to suppress the high electric field ( E-field) under the drain by dielectric RESURF. Second, a lower HK dielectric is at the bottom of the trench to promote the depletion of the N-buffer layer and P-substrate, which increases the N-buffer doping concentration and thus reduces ON-resistance. The overall vertical bulk E-field distribution is modulated by the E-field peak generated at the position of varying K dielectric, which greatly improves breakdown voltage (BV). An analytical model of BV and vertical E-field taking account of the influence of the VHK dielectric trench is presented. Simulation results show that the proposed VHK TR LDMOS is able to obtain a 30.2% higher BV and a lower 15.4% R _{ON, sp} than the CTR LDMOS. Moreover, the figure of merit (BV ² /R _ON,sp ) of VHK TR LDMOS has doubled further breaking the lateral silicon limit.

In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (RON,sp) of 28.53 mΩ∙cm2, which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV2/RON,sp of DG SJ-LDMOS is increased by 85.5 %.

A new theory about terminal technology is proposed for superjunction lateral double-diffused metal-oxide-semiconductor field effect transistors with multiple floating buried layers (MFBL SJ-LDMOS) based on the bulk electric field (E-field) modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the vertical voltage and bulk E-field distributions of MFBL SJ-LDMOS. The analytical formulas for the breakdown voltage (BV) and the vertical peak E-field of MFBL SJ-LDMOS are derived in the closed-form equations, which starts from a single floating buried layer for the vertical E-field modulation, extending this theory to predict the vertical E-field peaks and vertical voltage distributions between the MFBLs. Quantitative analytical description has been given to explain the bulk E-field modulation for the MFBL. Moreover, the optimal spacing and the maximum BV are procedurally predicted. All analytical results are well verified by the 3-D numerical simulations, proving the applicability of the method presented in other power devices with MFBL including MFBL LDMOS, MFBL lateral insulated gate bipolar transistor, and MFBL diode.