A novel superjunction (SJ) vertical UMOSFET with semi-insulating POly-crystalline silicon pillar (SIPOS SJ-UMOS) is proposed and its mechanism is investigated by TCAD simulations. In the off-state, the reshape effect of SIPOS pillars enhances the vertical electric field strength and weakens the lateral field component, which increases the breakdown voltage (BV). In addition, the highly doped N-pillars are allowed for the proposed device due to the enhanced depletion by the SIPOS pillars, which leads to a low specific ON resistance (R _ON,sp ). In the on-state, an accumulation layer is formed in drift region leading to an additional reduction in the R _ON,sp . Simulation results show that the RON,sp decreases 59%, and BV increases by 16.7%, simultaneously, breaking the SJ silicon limit, compared with those of a conventional SJ-UMOS with the same drift length. Moreover, the charge-imbalance endurance of SIPOS SJ-UMOS is also improved.

A new theory of lateral double-diffused MOS (LDMOS) by the folded-silicon substrate field-effect (FSLDMOS) with the complete 3-D REduced SURface Field (RESURF) is proposed in this paper for the first time. The analytical model for the relationship between the breakdown voltage (BV) and the specific ON-resistance (R _ON,sp ) of FSLDMOS is obtained, which breaks the limit relationship of the superjunction (SJ) LDMOS by applying three kinds of methods, including the additional electric-field modulation effect, majority carrier accumulation, and increasing the effective conduction paths simultaneously. In the analytical model, the influence of the structural parameters of the folded-drift and electric field modulation coefficients is considered. Besides, the optimal doping concentration of the folded-drift region for FSLDMOS is derived, which can give guidance for the dose of the folded-drift region. The results indicate that a new analytical expression for the relationship between the BV and R _ON,sp is obtained, which breaks the limit relationship of the SJ LDMOS by the complete 3-D RESURF. All analytical results are well verified by the simulation results conducted by ISE-TCAD, showing the validity of the presented model.

GaN-on-sapphire has recently attracted great attention for power electronics. Although plenty of efforts have already been made in this topic decades ago, but thorough evaluation on the buffer for $\ge$ 1200-V devices are, however, lacking. In this work, two promising buffers, i.e., AlGaN buffer and carbon-doped GaN buffer (C:GaN), are compared. The key results demonstrate that by replacing the AlGaN buffer with C:GaN buffer, the full-widths at half-maximums (FWHMs) of $\omega$ -rocking curves for (002) and (102) planes reduce from 785 and 2421 to 488 and 1240 arcsec, respectively, and the average sheet resistance $\textit{R}_{\Box}$ drops from 501 to 342 $\Omega$ / $\Box$ and its nonuniformity improves from 4.6% to 1.9%. The fabricated high-electron-mobility transistors (HEMTs) exhibit an optimized $\textit{R}_{{\text{ON}}}$ from 22.1 to 16.1 $\Omega \cdot$ mm, a more uniform off-state blocking capability, and an improved dynamic $\textit{R}_{{\text{ON}}}$ degradation from 104% to 50.4%. Capacitance and conductance analysis discovered that an extra group of deep traps is introduced by the AlGaN buffer. Further photoluminescence (PL) spectroscopy unveils a stronger yellow luminescence (YL), corresponding to a higher density of radiation-related defect recombination centers induced by the AlGaN buffer. Overall, this work unambiguously shows the carbon dopants, often used in GaN-on-Si epitaxy, can help to facilitate the commercialization of $\ge$ 1200-V HEMTs on sapphire in the future.

In this article, an innovative layout is introduced to reduce the stray inductance of the multichip power modules (MCPMs) through reverse coupling of current in parallel power loops, which effectively cancels out mutual inductance. A half-bridge silicon carbide (SiC) MOSFET power module was designed based on this novel layout. The fabricated SiC power module was experimentally validated, demonstrating a measured stray inductance of about 3.5 nH. Experimental results confirmed that the proposed module outperforms counterpart commercial SiC MOSFET power modules in terms of turn-off overshoot voltage and switching loss reduction, highlighting the advantage of the reverse-coupling current approach in enhancing power module performance. The principle of enhancing negative mutual inductance and dynamic current sharing in circuits through the reverse coupling parallel loops is discussed.

This paper introduces a fully symmetric layout for a 4-parallel SiC MOSFET half-bridge power module, wherein each power loop within the module exhibits physical and electrical symmetry along the x-axis, y-axis, and center. This symmetric layout ensures inductance consistency across the power loops, facilitating balanced current sharing within the power module. The imbalance ratio of inductance across the parallel loops in the proposed module is less than 2%. Further reduction in parasitic inductance is achieved by staggering the power terminals based on the symmetric layout. The optimized power module was fabricated and subjected to static and switching tests, demonstrating balanced current and thermal distribution. Additionally, the parasitic inductance of the proposed power module, calculated based on the double pulse test results, is found to be 3.54 nH, significantly lower than that of commercially available modules of the same rating.