This paper describes a capacitive touch-screen panel (TSP) readout IC that provides a reconfigurable SNR and frame rate with high noise immunity and touch sensitivity. The readout IC mitigates severe noise interference with a lock-in sensing architecture. In addition, a band-pass filtering effect by the TSP and charge amplifier further improves the noise immunity. A differential sensing scheme is employed to enhance the touch sensitivity and to reject a common-mode noise. A column-parallel incremental ΣΔ ADC is adopted to provide a high resolution and frame rate. Furthermore, a multiple sampling and averaging effect of the ADC enhances the noise immunity. The readout IC reconfigures its SNR and frame rate by adjusting the configurable resolution of the employed ADC. The test chip is fabricated in a 0.18 μm CMOS process and occupies a 2.2 mm 2 active area. The test chip achieves a 60 dB SNR and 200 Hz frame rate with a 12×8 TSP. The SNR can be adjusted from 40 dB to 67 dB, while the frame rate is then inversely scaled from 50 Hz to 6.4 kHz. The test chip supports a supply voltage range from 2.1 V to 3.3 V and consumes 6.26 mW from a 3.3 V supply.

This paper presents a fully synthesizable successive-approximation-register (SAR) analogto- digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and diagnosis. To implement the SAR ADC, a synthesizable voltage digital-to-analog converter (VDAC) and a rail-torail hybrid comparator are proposed in this paper. An inherited nonlinearity of the standard-cell-based VDAC is compensated by a histogram-based soft calibration which can be easily embedded in a waveform reconstruction module. In addition, an oversampling technique with a redundant error correction method is employed to realize the fully synthesizable design without a sample-and-hold (S/H) circuit. The proposed ADC was fabricated in 28-nm CMOS technology, occupying an active area of 0.002 mm2. The ADC achieves 5.39-bit effective-number-of-bit (ENOB) at 500-kS/s sampling rate. The power consumption of the ADC is 92.2 μW with a supply voltage of 0.5 V.

This paper presents a touch sensing analog front end (AFE) for capacitive touch-screen integrated into an ultra-thin display. Reduced distance between the touch screen and display causes large capacitive coupling, resulting in increased parasitic capacitance and reduced touch sensitivity. Display noise interference is worse due to the large coupling capacitance. Hence, it is a challenge to design an AFE capable of accurate and energy efficient sensing of a touch input in the integrated touch-screen panel. An adiabatic multi-driving method based on charge recycling is proposed to provide power-efficient stimulation of the touch-screen panel. Furthermore, in order to cancel out the display noise interference through the large parasitic capacitance, a fully differential touch sensing module is incorporated in the AFE. A correlated noise sampling (NS) is employed in the decoder stage for the multi-driving demodulation process. To further improve power efficiency, the sensing module is multiplexed in four ways while achieving an optimal conversion time per sample. The proposed AFE was implemented in a 180-nm CMOS process. The fabricated AFE shows 57.0-dB signal-to-noise ratio (SNR) at 120 fps while consuming 17.8 mW. Compared with power consumption of 19.9 mW expected with a conventional signal generation, the proposed adiabatic signal generator dissipates only 7.1 mW, exhibiting a power reduction of 64% due to the adiabatic driving method.

This letter presents an event-driven digital low-dropout regulator (DLDO) with an adaptive linear/binary two-step search achieving a fast transient response. A two-dimensional (2-D) circular shifting register (CSR) offers an adaptive linear-search regulation. When a large voltage droop occurs, the CSR activates a fast-tracking mode that provides immediate recovery from the droop. Once the linear search by the CSR is completed, a subrange successive-approximation register (Sub-SAR) conducts the binary-search regulation. The full-scale current range of the Sub-SAR is adaptively scaled by referencing the CSR, which reduces the number of searching steps and improves undershoot or overshoot caused by the binary-search operation. Ring amplifier based 1.5b continuous-time (CT) comparators and the asynchronous controllers realize the event-driven operation that breaks a tradeoff between transient response and sampling clock frequency. The proposed DLDO was fabricated in a 40 nm CMOS process. The DLDO can operate in an input voltage V _IN range from 0.6 to 1.2 V. When a load current step of 104.2 mA/1 ns was applied at a V _IN of 1.0 V, a droop-recovery time and a settling time were measured as 6 and 15 ns, respectively.

This brief presents a two-step hybrid integrator (TSHI) that can operate at a wide supply voltage range, which is demonstrated with a third-order ${\Delta \Sigma }$ analog-to-digital converter (ADC). The proposed TSHI consists of a zero-crossing-detector (ZCD)-based integrator and an inverter-based integrator. In the coarse-integration step, the ZCD-based integrator performs a fast integration without concern for overshoot or detection delay issues. In the fine-integration step, the inverter-based integrator performs the residual integration with high accuracy. Hence, the TSHI provides fast and accurate integration process. In addition, the TSHI supports trade-off between voltage-scalable bandwidth and power consumption for an energy efficient operation of Internet-of-Things sensor nodes, owing to the scalable operation of the ZCD and inverter. The proposed ${\Delta \Sigma }$ ADC is fabricated in a 65-nm LP CMOS process, and the active area is 0.38 mm². The fabricated ADC operates at supply voltages from 0.4 to 1 V. Depending on the supply voltage and sampling frequency, the power consumption and bandwidth of the ADC can be scaled from 12.7 to $948~{\mu }{\mathrm{W}}$ and from 7.5 to 400 kHz, respectively. The ADC maintains an SNDR higher than 60 dB within the operating supply range.

This article proposes a fully integrated hybrid low-dropout regulator (HLDO) that features an ultralow dropout and a highly improved transient response. This HLDO incorporates a residue-current-locked loop (RLL) that realizes joint regulation using a residue-compensating analog LDO (RLDO) and residue-triggered asynchronous digital LDO (DLDO). The RLDO supplements the residual current to compensate for the current quantization error (CQE) of the DLDO, thus eliminating the limit cycle oscillation (LCO) and improving the power supply rejection compared to standalone DLDOs. Moreover, the RLDO uses a bounded residue control (BRC) scheme that achieves sub-50-mV dropout regulation based on the RLL. The RLDO based on a flipped-voltage-follower (FVF) is equipped with a droop-edge injection scheme, and it improves the fast transient response against a heavy load by promptly triggering the self-clocked DLDO. Residue-driven DLDO control is realized using asynchronous pointer-shift registers (PoSRs) so that the DLDO can respond rapidly without the use of any high-frequency clock. The prototype implemented using a 65-nm CMOS process achieves a 76-mV voltage droop and an 8.2-ns settling time against a load current step of 80 mA/0.5 ns with a 20-mV dropout voltage. The prototype demonstrates load regulation of 0.06 and less than 0.01 mV/mA with a dropout voltage of 20 and 50 mV, respectively, at a 1-V input.