A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs _rms integrated jitter. This translates to a FoM _J of -240.5 dB, which is the best among the reported fractional-N PLLs.

Time-based controllers are well suited for implementing both single- and multi-phase wide bandwidth high switching frequency pulsewidth modulation (PWM)-based dc-dc converters. They also consume very little quiescent current but their light load efficiency is severely degraded by switching losses. We explore pulse frequency modulation (PFM) that is commonly used to improve light load efficiency in voltage-mode controllers and extend its operation to time-based controllers. To maintain high efficiency even in the presence of dynamic load variations, we present techniques to perform automatic and seamless switching between PWM/PFM modes. Fabricated in a 65-nm CMOS, the prototype buck converter using the time-based PWM/PFM control achieves 90% peak efficiency and >80% efficiency over a load current range of 2-800 mA. Output voltage changes by less than 40 mV during PWM to PFM transitions.

This article proposes a fully integrated hybrid low-dropout regulator (HLDO) that features an ultralow dropout and a highly improved transient response. This HLDO incorporates a residue-current-locked loop (RLL) that realizes joint regulation using a residue-compensating analog LDO (RLDO) and residue-triggered asynchronous digital LDO (DLDO). The RLDO supplements the residual current to compensate for the current quantization error (CQE) of the DLDO, thus eliminating the limit cycle oscillation (LCO) and improving the power supply rejection compared to standalone DLDOs. Moreover, the RLDO uses a bounded residue control (BRC) scheme that achieves sub-50-mV dropout regulation based on the RLL. The RLDO based on a flipped-voltage-follower (FVF) is equipped with a droop-edge injection scheme, and it improves the fast transient response against a heavy load by promptly triggering the self-clocked DLDO. Residue-driven DLDO control is realized using asynchronous pointer-shift registers (PoSRs) so that the DLDO can respond rapidly without the use of any high-frequency clock. The prototype implemented using a 65-nm CMOS process achieves a 76-mV voltage droop and an 8.2-ns settling time against a load current step of 80 mA/0.5 ns with a 20-mV dropout voltage. The prototype demonstrates load regulation of 0.06 and less than 0.01 mV/mA with a dropout voltage of 20 and 50 mV, respectively, at a 1-V input.

This study examines how Chief Executive Officer (CEO) overconfidence affects profitability. Using United States data from 1992 to 2010, we find that firms with overconfident CEOs have a greater return on net operating assets (RNOA). To identify the sources of this higher performance, RNOA is partitioned into profit margin and asset turnover. This Dupont analysis reveals that higher RNOA of firms with overconfident CEOs comes from profit margin and is not associated with asset turnover. Our results also show that the earnings components of firms having overconfident CEOs better predict future earnings change. The results are robust to the different definitions of CEO overconfidence and profitability. Additional analyses show that CEO overconfidence is positively related with stock performances proxied by abnormal stock returns. Overall, our results suggest that CEO overconfidence is an important factor that contributes to higher and predictable performance of firms.

Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a baud-rate ROO receiver that can turn on in just 10 ns (~120 UI). Baud-rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER < 10⁻¹² and achieves a >30-MHz JTOL corner, 377 fsrms recovered clock jitter, and 3.8-pJ/bit energy efficiency.