The current work is devoted to chaos oscillator employment in digital communication systems for IoT applications. The paper presents a comparative performance analysis of two different chaos data transmission systems: frequency-modulated chaos shift keying (FM-CSK) and quadrature chaos phase-shift keying (QCPSK), and a comparison to their non-chaotic counterparts: frequency-shift keying (FSK) and quadrature amplitude modulation (QAM). For both chaotic communication systems, the Vilnius oscillator and substitution method of chaotic synchronization are chosen due to simple circuitry implementation and low power consumption properties. The performance of the systems in the fading channel with additive white Gaussian noise (AWGN) is evaluated. Also, the systems’ performance in the case phase noise is investigated, and the benefits of chaotic waveforms employment for data transmission are demonstrated.

The current work presents a novel digital chaotic communication system with antipodal chaotic shift keying modulation, implemented in a field-programmable gate array (FPGA). Such systems provide high security on the physical communication level and can be used in wireless sensor network systems. A modified Chua circuit chaos generator and error linear feedback chaotic synchronization are implemented in FPGA and used to develop a chaotic communication system with digital transmitter and receiver an analog in-between signal transmission. Additionally, a validated mathematical model of the communication system prototype is created in the Simulink environment, which is used to compare the performance of the prototype and its nodes with the simulation and simplify its development. The performance is evaluated using simulation with the additive white Gaussian noise channel and analyzing the bit error ratio.

The current work is focused on studying the performance of the Pecora–Carroll synchronization technique to achieve synchronization between the analog and discrete chaos oscillators. The importance of this study is supported by the growing applications of chaotic systems for improving the security of data transmission in various communication layers, primarily on the physical layer. The hybrid analog-discrete approach of implementing chaos oscillators opens new possible communication schemes for wireless sensor network (WSN) applications. The analog implementation of chaos oscillators can benefit the simpler sensor node (SN) integration, while the discrete implementation can be used on the gateway. However, the core of such chaos-based communications is synchronizing analog and discrete chaos oscillators. This work studies two key parameters of analog-discrete chaotic synchronization: chaotic synchronization noise immunity and synchronization speed. The noise immunity study demonstrates the quality of synchronization at various noise levels, while the synchronization speed demonstrates how quickly the analog-discrete synchronization is achieved, along with how quickly the two systems diverge when synchronization is no longer present. The two studies use both simulation-based and hardware-based approaches. In the simulation case, the analog oscillator’s circuit is modeled in LTspice XVII, while in the hardware case, the circuit is implemented on the PCB. In both simulation and hardware studies, the discrete model of the oscillator is implemented in MATLAB R2023b. The studies are performed for two pairs of different chaos oscillators to widen the proposed approach application potential: the Vilnius and RC chaos oscillators. The oscillators have been selected due to their simplicity and similar dynamic behavior for model-based and electrical circuit implementation. The proposed approach also allows us to compare the synchronization of different oscillators in the analog-discrete implementation.

This manuscript presents an experimental study of Quadrature Chaos Shift Keying (QCSK) as a means to tighten the physical layer security of Internet of Things (IoT) communication. Our study examines the characteristics and operational aspects of chaos oscillators, prioritizing low-power functionality, resilient chaotic oscillations, and resistance to parameter variations and noise. This study emphasizes the key role of chaos oscillators in enhancing IoT security, showcasing their potential to ensure data integrity. The findings elucidate the dynamics and synchronization stability of the selected oscillators, providing insights into their suitability for secure communication systems. This comprehensive analysis contributes to advancing secure communication methodologies for the expanding landscape of wireless sensor networks in the Internet of Things, underscoring the significance of chaos oscillators in ensuring robust and secure data transmission.

Using chaos for communication can provide more robust channel security, covert transmission, and inherent support for spread-spectrum modulation. Although numerous studies have explored this technology, its practical deployment remains limited due to substantial hardware demands, complex signal processing, and a lack of efficient modulation methods for chaotic signals. In this study, a novel chaotic digital communication system is proposed and studied. A prototype of a frequency-modulated antipodal chaos shift keying (FM-ACSK) system is implemented on an Intel Cyclone V field-programmable gate array (FPGA) along with a complete mathematical model using Matlab R2022a Simulink software. Using FPGAs to implement chaotic oscillators avoids analog system problems such as component drift and high thermal instability while providing determined system parameters, rapid prototyping, and high throughput. The employment of FM over a chaotic modulation layer provides a passband operation (currently at an intermediate frequency of 10.7 MHz) while adding the benefits of carrier frequency offset robustness and constant signal envelope. Within this study, the robustness of FM-ACSK to white noise in the channel was evaluated using bit error rate, which was tested through hardware experiments and simulations. The results show the feasibility and potential performance limitations of this approach to chaotic communication system design.

The chaotic systems are one of the most important areas that increasing the popularity and are actively used in several fields. One of the most essential structures in chaotic systems is chaotic oscillator which generates chaotic signals. IQ-Math and floating point number systems are one of the preferred number standards. Presented in this study, the Modified Chua chaotic oscillator has been designed to work on FPGA chips using fixed point and floating point number systems. Euler numeric algorithm has been used for the design of the Modified Chua chaotic oscillator. The first section of the study, Modified Chua chaotic system based on fixed point has been composed the model in the Matlab Simulink and transformed to VHDL with the help of Matlab HDL Coder Toolbox. The second section of the study, Modified Chua chaotic oscillator has been designed with VHDL based on floating point. Modified Chua chaotic oscillators which are composed with two different number standards have been tested using Xilinx ISE Design Tools in VHDL. Modified Chua chaotic oscillators which have two different numbers standards and designed, are synthesized for Virtex-6 on ML605 FPGA development board with Xilinx ISE Design Tools 14.2 program. Values that are achieved from the process of synthesizing and maximum operating frequency have been presented. As a result, the study has obtained that fixed point number standard maximum operating frequency is 50.242 MHz and floating point number standard maximum operating frequency is 273.631 MHz.