The successful implementation of perovskite light-emitting diodes (PeLEDs) in advanced displays and lighting has proven to be challenging because of the inferior performance of blue devices. Here, we point out that a strained system would lead to the quasi-degenerate energy state to enhance the excited-state transition due to the formation of double-polarized transition channel. The tensile strained structure also brings about a synergetic control of the carrier dynamics in virtue of lattice structure deformation and reduced dimensional phase regulation to promote carrier population in large bandgap domains and to realize near-unit energy transfer from the large bandgap phases to the emitter phases. Accordingly, high external quantum efficiencies of 14.71 and 10.11% are achieved for the 488- and 483-nanometer PeLEDs. This work represents a versatile strategy using a strained system to achieve enhanced radiative emission for the development of efficient PeLEDs.

Both fluorination and oxidation have been employed to passivate defects in indium-gallium-zinc oxide thin-film transistors, leading to enhanced device attributes. It is presently reported that the former is more effective than the latter, requiring shorter process time (hence improved manufacturing efficiency), resulting in reduced initial defect population (hence enhanced scalability), and more robust resistance against process- and stress-induced defect generation (hence improved reliability). It is determined that the fluorine drive-in heat treatment is best conducted in an oxidizing atmosphere.

Reported presently are two design approaches to improve the performance of an electrothermal in-plane microactuator with “chevron” beams. One incorporates beams with uniform cross sections but nonuniform lengths or tilt angles to accommodate the thermally induced expansion of the “shuttle”; the other incorporates beams with nonuniform cross sections to widen the high-temperature “expansion” zones. It is derived analytically, verified using finite-element simulations, and tested by microfabricating actuators occupying a constrained device area that the incorporation of one or the other proposed features leads to an improved performance figure-of-merit, defined to be the product of the actuation displacement and force. An increase in the figure-of-merit by up to 65% per beam has been measured.

The large‐area low‐temperature processing capability and versatile characteristics of amorphous oxide semiconductor (AOS) thin‐film transistors (TFTs) are highly expected to promote the developments of next‐generation displays, 3D integrated circuit (3DIC), flexible chips, and electronics. However, the abundant native defects in AOSs engrain an inherent trade‐off between high mobility and trustworthy stability in AOS TFTs, fundamentally limiting the performance metrics and integration scale of oxide‐based electronics. To surmount this obstacle, the bilayer AOS channel is highly expected to combine the merits of diversified AOSs, while the efficiency of such an AOS “heterojunction” is debatable. This work systematically compares the TFTs based on amorphous InGaZnO (a‐IGZO), amorphous InZnO (a‐IZO), and a‐IZO/a‐IGZO bilayer. The active cation interaction between metal‐oxide semiconductors gives rise to a mixed AOS layer rather than a heterojunction channel, corresponding to moderate performance metrics. Such a spontaneous cation interdiffusion is effectively prevented using a dense metal‐oxide dielectric interlayer, aluminum oxide (AlO_x). The sharpened interface effectively forms an abrupt metal‐oxide heterojunction, while the electron can still tunnel through the ultrathin AlO_x to create a quantum well of 2D electron gas (2DEG). The overall performance and reliability of multilayer AOS TFT are synergistically enhanced using the proposed abrupt metal‐oxide heterojunction architecture.

The resistivity of an indium-gallium-zinc oxide (IGZO) thin film was found to depend on not only the conditions of its thermal annealing but also the oxygen-permeability of the cover film during the heat treatment. Based on this observation, a technology for constructing a bottom-gate IGZO thin-film transistor with annealing-induced source and drain (S/D) regions is proposed and demonstrated. The S/D and channel regions with this device architecture are capped, respectively, by impermeable and permeable covers. During a subsequent heat treatment in an oxidizing atmosphere, the resistivity of the S/D regions is greatly reduced; while the channel region, being exposed to the oxidizing atmosphere through the permeable cover, retains its highly resistive character. The permeable cover protects the channel region by serving additionally as an inherent back-channel etch-stop during the etching of the impermeable cover. No patterning is needed to realize this etch-stop, implying a lower manufacturing cost.

Incorporated with the annealing-induced source/drain (S/D), elevated-metal metal-oxide (EMMO) thin-film transistor (TFT) was proposed to provide an etch-stop (ES) layer while retain a small device size for high-resolution displays, which could not be combined in conventional TFT architectures. The “defect-populated” S/D and “defect-free” channel enabled the high performance metrics: a competitive field-effect mobility of ~14 cm ² /Vs; an extremely low off-current of ~10 ^-18 A; an impressive on/off ratio of ~10 ¹² ; and the superior reliability against temperature, bias and current stresses.