The large‐area low‐temperature processing capability and versatile characteristics of amorphous oxide semiconductor (AOS) thin‐film transistors (TFTs) are highly expected to promote the developments of next‐generation displays, 3D integrated circuit (3DIC), flexible chips, and electronics. However, the abundant native defects in AOSs engrain an inherent trade‐off between high mobility and trustworthy stability in AOS TFTs, fundamentally limiting the performance metrics and integration scale of oxide‐based electronics. To surmount this obstacle, the bilayer AOS channel is highly expected to combine the merits of diversified AOSs, while the efficiency of such an AOS “heterojunction” is debatable. This work systematically compares the TFTs based on amorphous InGaZnO (a‐IGZO), amorphous InZnO (a‐IZO), and a‐IZO/a‐IGZO bilayer. The active cation interaction between metal‐oxide semiconductors gives rise to a mixed AOS layer rather than a heterojunction channel, corresponding to moderate performance metrics. Such a spontaneous cation interdiffusion is effectively prevented using a dense metal‐oxide dielectric interlayer, aluminum oxide (AlO_x). The sharpened interface effectively forms an abrupt metal‐oxide heterojunction, while the electron can still tunnel through the ultrathin AlO_x to create a quantum well of 2D electron gas (2DEG). The overall performance and reliability of multilayer AOS TFT are synergistically enhanced using the proposed abrupt metal‐oxide heterojunction architecture.

We herein demonstrate a self-aligned top-gate (SATG) coplanar amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) technology, with the gate length ( ${L}_{\text {g}}$ ) down-scaled to 97 nm, and gate insulator (GI) AlOx to 4 nm (equivalent oxide thickness = 2.4 nm). The fabricated TFT exhibits a large on-current ( ${I} _{\text {ON}}$ ) of $17.9~\mu \text{A}/\mu \text{m}$ , a high on/off current ratio over 109, a positive threshold voltage ( ${V} _{\text {TH}}$ ) of 0.07 V, and a minimum drain-induced barrier lowering (DIBL) of 77 mV/V. The well-maintained performances of the TFTs even in the nanoscale regime can be ascribed to the abrupt homojunction at source-drain sides and high-quality of ultrathin gate insulator of AlOx by atomic layer deposition (ALD). With the excellent scaling metrics and compatibility with modern integrated circuit (IC) process, the developed SATG a-IGZO TFT technology is compatible with the back-end-of-line(BEOL) and 3D integrations of advanced ICs.

The carrier transport properties in amorphous oxide semiconductor (AOS) heterojunction thin-film transistors (TFTs) are investigated by using dual gates to control the channel of bilayer AOSs. The mobility of such heterojunction channel exhibited distinct dependences on top-gate (TG) voltage ( $V_{\text {TG}}$ ) and bottom-gate (BG) voltage ( $V_{\text {BG}}$ ) The mobility was well maintained in TG mode, where $V_{\text {TG}}$ was in line with the build-in electric field of the electron potential well (PW) formed at the heterojunction interface. In contrast, an increased $V_{\text {BG}}$ gradually reduced the high mobility to the level of a single layer channel, since a high $V_{\text {BG}}$ in the opposite direction of PW could eliminate the PW. This experimentally clarifies that the high-mobility transport path of AOS heterojunction channel locates in the interface PW and its operation demands a proper gate field direction. This were directly consolidated by the disclosed unique capacitance-voltage characteristics.

A deep sub-micron self-aligned bottom-gate (SABG) amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) technology was developed. The implementation of a backside exposure technique enables the realization of a self-aligned structure, while an argon (Ar) plasma treatment minimizes the source/drain resistance ( R _SD ). High-performance metrics were well maintained on the fabricated SABG a-IGZO TFT with a channel length of 302 nm (effective channel length of 208 nm), including a low off-state current around 10 ^-14 A/μm, a subthreshold swing of 103.8 mV/dec, a decent mobility of 7.48 cm ² /V∙s, a minor drain-induced barrier lowering (DIBL) of 41.5 mV/V, a negligible channel length shrinking (Δ L ) of 47 nm and a record-low R _SD of 0.86 Ω∙cm among self-aligned (SA) transistors. Such remarkable scalability and manufacturing capability pave a new cost-effective way for high integration-density oxide electronics.