Physical systems may be carried out in both hardware and software. Hardware is based on implementing appropriate logic functions in FPGA structures connected with a physical layer of cyber-physical systems (CPSs). Effective technology mapping of these functions in FPGA structures is directly connected with logic synthesis. Thus, in the case of CPSs, we can talk about cyber-physical synthesis. The effectiveness of this synthesis is key from the point-of-view of designing CPSs. This paper focuses on the methods aiming at shortening synthesis time of circuits carried out in FPGA circuits. The proposed synthesis methods stem from an original way of a function representation enabling to quick search for appropriate decompositions. This paper presents a series of original methods. They include enabling for a quick relocating of variables between bound and free sets, time effective and multilevel technology mapping of multi-output function, and techniques of quick efficiency assessing of technology mapping taking non-disjoint decomposition into account. The methods are the basis of the algorithms implemented in the author's synthesis tools such as dekBDD and MultiDec. The effectiveness of the proposed methods was proved via experiments. The main contribution of the paper in the area of cyber-physical synthesis is proposing effective methods of carrying out a hardware layer cyber-physical synthesis that uses the FPGA circuits.

Decomposition-based logic synthesis for PAL-based CPLDs: The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

The article discusses a synthesis strategy aimed at reducing power consumption consumed by logic structures implemented in FPGAs. The essence of the method is to carry out multioutput function decomposition, which takes into account the problem of dynamic power reduction. The article presents several techniques leading to such a reduction: preliminary ordering of variables taking into account the probabilities of occurrence of the value 1 for individual variables, reduction of the number of LUTs by limiting the number of bound functions, and in particular bicoding or appropriate unicoding taking into account the need to reduce power for the implementation of multioutput functions. These techniques have been combined into a coherent synthesis strategy called PowerdekBDD, which is an extension of the DekBDD strategy, which is the result of many years of work in the area of logic synthesis using BDD graphs. The article contains the results of experiments confirming the effectiveness of the presented strategy.

The paper presents the methods of searching for non-disjoint decomposition using BDD. Non-disjoint decomposition is a generalization of a classic decomposition model. Its main advantage is the reduction of necessary logic blocks needed to implement bound blocks. The essence of non-disjoint decomposition is based on searching for input variables that may fulfill the role of bound functions. The authors present the methods of searching for these variables in one or multi-root BDD diagrams. DekBDD enables to carry out non-disjoint decomposition on benchmark circuits. In the unit, entitled ‘Experimental results’, the number of necessary LUT blocks needed to implement multioutput function with the usage and without using non-disjoint decomposition, was determined for selected benchmarks. Moreover, the number of bound functions and the number of found ‘switching’ variables (non-disjoint decompositions) were given in the table. This attitude enables to determine the degree of optimization of a gained logic structure thanks to non-disjoint decomposition.