One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

Physical systems may be carried out in both hardware and software. Hardware is based on implementing appropriate logic functions in FPGA structures connected with a physical layer of cyber-physical systems (CPSs). Effective technology mapping of these functions in FPGA structures is directly connected with logic synthesis. Thus, in the case of CPSs, we can talk about cyber-physical synthesis. The effectiveness of this synthesis is key from the point-of-view of designing CPSs. This paper focuses on the methods aiming at shortening synthesis time of circuits carried out in FPGA circuits. The proposed synthesis methods stem from an original way of a function representation enabling to quick search for appropriate decompositions. This paper presents a series of original methods. They include enabling for a quick relocating of variables between bound and free sets, time effective and multilevel technology mapping of multi-output function, and techniques of quick efficiency assessing of technology mapping taking non-disjoint decomposition into account. The methods are the basis of the algorithms implemented in the author's synthesis tools such as dekBDD and MultiDec. The effectiveness of the proposed methods was proved via experiments. The main contribution of the paper in the area of cyber-physical synthesis is proposing effective methods of carrying out a hardware layer cyber-physical synthesis that uses the FPGA circuits.

The main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-based FPGA. New elements of the proposed synthesis strategy include: an original method of function decomposition, non-disjoint decomposition, and technology mapping dedicated to configurability of logic blocks. The aim of all of the proposed synthesis approaches is the sharing of appropriately configured logic blocks. Innovation of the methods is based on the way of searching decomposition, which relies on multiple cutting of an MTBDD diagram describing a multi-output function. The essence of the proposed algorithms rests on the method of unicoding dedicated to sharing resources, searching non-disjoint decomposition on the basis of the partition of root tables, and choosing the levels of diagram cutting that will guarantee the best mapping to complex logic blocks. The methods mentioned above were implemented in the MultiDec tool. The efficiency of the analyzed methods was experimentally confirmed by comparing the synthesis results with both academic and commercial tools.