Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

Heterogeneous integration of III-V materials onto silicon photonics has experienced enormous progress in the last few years, setting the groundwork for the implementation of complex on-chip optical systems that go beyond single device performance. Recent advances on the field are expected to impact on next generation optical communications to attain low power, high efficiency and portable solutions. To accomplish that aim, intense research on hybrid lasers, modulators and photodetectors is being done to implement optical modules and photonic integrated networks with specifications that match the market demands. Similarly, important advances on packaging and thermal management of hybrid photonic integrated circuits (PICs) is currently in progress. In this paper, we report our latest results on hybrid III-V on Si transmitters, receivers and packaged optical modules for high-speed optical communications. In addition, a review of recent advances in this field will be provided for benchmarking purposes.

We design and fabricate the packaging of 128 × 128 silicon photonic MEMS switch device using through glass via (TGV) interposer and pitch reducing fibre array. The switch device contains 16384 MEMS switch cells and 272 grating couplers spaced at 63.5 μm in a compact footprint of 17.4 mm × 16 mm. The apodised grating couplers designed for 1300 nm have an insertion loss of 2.5 dB/facet at 10° coupling angle. The 0.5 mm thick glass interposer contains 512 electrical vias while the pitch reducing optical coupling array is polished to 40° for planar coupling.

Adiabatic techniques are well-known tools in multi-level electron systems to transfer population between different states with high fidelity. Recently, it has been realized that these ideas can also be used in ultracold atom systems to achieve coherent manipulation of the atomic centre-of-mass states. Here, we present an investigation into a realistic setup using three atomic waveguides created on top of an atom chip and show that such systems hold great potential for the observation of adiabatic phenomena in experiments.

This paper investigates the use of glass interposers as a scalable and cost-effective solution for co-packaged electronic-photonic systems, with a focus on optimizing thermal management and electrical transmission. The thermal management study is carried out through design, assembly and characterization of a thermal test vehicle. The thermal test vehicle is used to study the heat dissipation in glass interposers by varying the Through Glass Via (TGV) pitch (100 μm to 400 μm). The outcomes indicate a maximum surface temperature rise of 2.9 °C, which is also confirmed by finite element method simulations. Moreover, the simulations also suggest that changes in TGV pitch below 100 μm do not significantly impact the temperature variation. The electrical transmission through the glass interposer package is investigated using three different design scenarios (Transmission Lines on Glass, Glass Interposer and Electrical Test Vehicle). The RF performance of each design is studied up to 40 GHz to analyze the losses incurred by different components in the package. In conclusion, this work presents an optimized electrical design for the test vehicle. By employing strategically designed geometries for TGVs, microvias, and ball grid array (BGA) pads, we achieved a significant reduction in insertion loss of approximately 11 dB at 40 GHz. This design approach can be compatible with 2.5D and 3D integration schemes, enabling high-density and high-performance electronic-photonic packages.