This paper presents a systematic method for decreasing the amount of transconductors used by an operational transconductance amplifier-capacitor (OTA-C) filter to decrease the power consumption and the active area. An OTA with a local-feedback linearized technique and a transconductance booster is proposed based on the presented method. The proposed OTA combines current division with source degeneration to enhance linearity and implement low transconductance. This topology enables the proposed OTA to drive multiple integration capacitors without an additional output stage. The OTA-based circuit realizes low power consumption by operating under a weak inversion at a supply voltage of 1 V. Thus, a fifth-order ladder-type low-pass Butterworth OTA-C filter is implemented for the acquisition of electrocardiograph signals. The proposed method is validated using a prototype fabricated through a 1P6M 0.18-μm CMOS process. Results show that in ECG signal acquisition, the proposed filter has a signal bandwidth located within 250 Hz, a dynamic range of 61.2 dB, and a power consumption of 41 nW to achieve a figure-of-merit of 5.4 × 10 ^-13 . The active area of the filter is 0.24 mm ² .

In the industrial Internet of Things, the network time protocol (NTP) can be used for time synchronization, allowing machines to run in sync so that machines can take critical actions within 1 ms. However, the commonly used NTP mechanism does not take into account that the network packet travel time over a link is time-varying, which causes the NTP to make incorrect synchronization decisions. Therefore, this paper proposed a low-cost modification to NTP with clock skew compensation and adaptive clock adjustment, so that the clock difference between the NTP client and NTP server can be controlled within 1 ms in the wired network environment. The adaptive clock adjustment skips the clock offset calculation when the NTP packet run trip time (RTT) exceeds a certain threshold. The clock skew compensation addresses the inherent issue that different clocks (or oscillators) naturally drift away from each other. Both adaptive clock adjustment and clock skew compensation are environment dependent and device dependent. The measurement result in our experimental environment shows that the when the RTT threshold is set at 1.7 ms, the best synchronization accuracy is achieved.

With the vigorous development of industrial automation and the Internet of things, the transmission of data is more dependent on immediacy, so network devices have higher and higher requirements for time synchronization accuracy. The clock source of common network devices is provided by the transistor oscillator in the server, but the oscillator will change with factors such as aging and temperature, and it cannot be guaranteed that the oscillator in the server will work at the same frequency. Time synchronization can be achieved by technologies such as IRIG-B, NTP, or IEEE 1588 (PTP), but the hardware cost of building IRIG-B is high, and NTP has the lowest cost, but it can only provide time accuracy from milliseconds to microseconds. PTP can provide sub-microsecond or even nanosecond time precision. It is a system of time synchronization mechanisms through Ethernet transmission. In this article, we first propose a time synchronization system using the development board and PDP protocol. On the Xilinx Zynq-7000 SOC platform of Petalinux, we implement the hardware solution of Linux PTP. The hardware time stamp is 20 ns. To improve the accuracy, the congenital frequency error between the oscillators must be considered. Therefore, a PTP auxiliary time stamp with dynamic frequency compensation is proposed and designed into a chip. Experimental results show that at 45 nm (TN40G) it can operate at 370 MHz and achieve 2.7 ns resolution, which can be applied to more demands.

In the generalized spatial modulation (GenSM) multiple input multiple output (MIMO) system, each block of data bits is mapped to a set of spatially multiplexed (SMX) symbols and an index of transmit antenna combination (TAC) of active antennas. The difficulty for the GenSM MIMO receiver is to detect the SMX symbols and TAC index simultaneously. Recently, we applied the conventional sphere decoding algorithm (SDA) successively to achieve the exact maximum likelihood detection (MLD) of GenSM MIMO signals. The SDA scheme suffers from variable computational complexity and leads to hardware detectors with variable throughput rate. Instead, fixed-complexity tree search algorithms, e.g., reduced fixed sphere decoding (rFSD), with nearly MLD performance are employed to facilitate hardware implementation. Here, we propose to apply the rFSD successively and design a hardware architecture for detecting GenSM MIMO signals under the scenario of 5 transmit antennas, 2 transmit radio frequency chains, 4 receive antennas, and 64-QAM SMX symbols. The VLSI implementation results under the TSMC 90nm CMOS technology reveal that our architecture requires 276.7K gates and provides detection throughput 1.613 Gbps, while operating at 322.6 MHz. Compared with other related architectures, our architecture provides higher detection throughput rate and is of better hardware efficiency.

This study presents a low‐power energy‐harvesting circuit with error‐correction demodulation for body sensor networks with radio‐frequency identification (RFID) systems. The proposed circuit adopts a new structure that facilitates the demodulation of amplitude‐shift‐keying (ASK) signals, and it includes a power unit consisting of a wake‐up circuit and a power‐on‐reset control circuit. The wireless bio‐signal acquisition system and the digital processor are implemented on a field‐programmable gate array to demonstrate the proposed RFID tag. The proposed energy‐harvesting circuit can substantially decrease the capacitance used by the demodulator circuit and the wake‐up circuit to as low as 14 pF. Moreover, a detection circuit and a correcting circuit are utilised to reduce the bit error rate of decoding. The wireless bio‐signal acquisition scenario is also set up and the communication signal between reader and tag is measured to demonstrate the system that can be employed in body sensor network with the healthcare system. The chip was implemented in complementary metal–oxide–semiconductor 0.18 μm technology. The sensitivity of this work is − 13 dBm. The pulse width error can be reduced to <1% by the error‐correction demodulator to fit the EPC Gen‐2 standard.

Soft-input soft-output (SISO) detector for the iterative detection and decoding of coded spatial modulation (SM) signals needs to compute the extrinsic bit log-likelihood ratio (LLR) associated with each detected bit. The maximum logarithmic maximum a posteriori (max-log-MAP) detector is known to perform closely to the optimal logarithmic maximum a posteriori (log-MAP) detector with much lower computational complexity. In this paper, we first apply several mathematical tricks to derive a new and low-complexity algorithm for the max-log-MAP detector. The proposed algorithm features a new tree pruning technique to visit few lattice points and a smart list administration technique to retain a max-log-MAP detector. By following the proposed algorithm, we then design a hardware architecture for SISO detection of coded SM signals over the scenario of 64-QAM symbols, 8 transmit antennas, and 4 receive antennas. Under the TSMC 40 nm CMOS technology, the VLSI implementation results reveal that our architecture requires 46.4K gates and leads to detection throughput 450 Mbps, while operating at clock frequency 400 MHz and consuming power 46 mW. Being the first hardware architecture for SISO detection of coded SM signals, our proposed low-cost max-log-MAP detector is very attractive.