Electrical characteristics of scaled 3-D nand cells for next-generation node development were predicted using transfer learning with limited data. The nand cell structure parameters were considered as the inputs, and outputs included key electrical characteristics, such as cell ${V}_{t}$ , the difference in ${V}_{t}$ between the initial and programming states ( $\Delta {V}_{t}$ ), subthreshold swing (SS), and on-current ( ${I}_{\text {ON}}$ ). A multilayer perceptron (MLP) model comprising four hidden layers and focusing on large nand cells (25 nm gate length) with 2000 data points served as a pre-trained model. The transfer model leveraged pre-trained knowledge to predict the electrical characteristics of smaller cells (19 nm gate length) with 500 data points without weight and bias training. Evaluation of test data exhibited remarkable accuracy with both the mean and standard deviation below 3%, proving the model’s effectiveness despite limited data. In addition, a comprehensive evaluation was conducted by comparing the performance of the model with variations in the dataset size and the presence of transfer learning, highlighting the effectiveness and advantages of transfer learning. Transfer learning could provide detailed structure information of the next node for engineers and expedite device development, resulting in significant time and cost savings.

The enhancement of program efficiency is essential for fast NAND cell operation. However, it is difficult to simultaneously consider many factors, such as structural parameters and trap characteristics, having complex relationships. To overcome these problems, we proposed a neural network (NN)-applied optimization method. First, an optimal network structure was selected by comparing the network performance and learning time. The selected network accurately predicted the threshold voltages of the 21 states of a single NAND cell within a second. Next, an optimization method to improve program efficiency is suggested. The improved NAND cell structure is obtained using a trained NN and numerical method. Here, the optimization required only a few minutes for one optimization process and could consider all parameters simultaneously. Finally, the optimized NAND cell was evaluated using a technology computer-aided design (TCAD) simulation, and its program efficiency was verified. This study shows a specific example of machine learning applied to the semiconductor area, especially in NAND flash memory.

Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R²) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.

A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (V_th) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the V_th window between the erase and program V_th. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the V_th window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (N_TD and N_TA) and their standard deviations (σ_TD and σ_TA) were found to most strongly impact the V_th window. As they increased, the V_th window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the V_th window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash.

We propose a novel approach that combines machine learning (ML) and Pareto optimization to simultaneously enhance the program efficiency and disturbance of 3D-NAND flash memory. The relationship between program pulse (PP) shapes and threshold voltage shifts has never been investigated owing to the presence of numerous PP shapes. The complex relationship is modeled rapidly and quantitatively by leveraging ML. A multiobjective optimization problem is designed to consider the trade-off in program efficiency and disturbance. Pareto optimization facilitates determining PP shapes that achieve optimal solutions between maximizing program efficiency and minimizing program disturbance. The Pareto front provides practical and intuitive candidates for determining optimal PP shapes. Experimental results confirm that the program efficiency and disturbance can be enhanced by 14%–22% and 5%–40%, respectively. The ML-based Pareto optimization has the potential to vary the pulse conditions for desired operations in 3D-NAND flash, which is the biggest nonvolatile memory market in the semiconductor industry.