A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) is proposed based on fully calibrated Technology Computer-Aided Design (TCAD) simulation. Highly doped punch-through stopper (PTS) layers are generally used to suppress trpbt. Unfortunately, trpbt is still a fatal failure factor in electrical performance degradation when the source/drain (S/D) recess is overetched. Moreover, the proposed TIS scheme prevents the diffusion of S/D dopants toward the PTS region beneath the bottom gate, thereby inhibiting the formation of trpbt. Furthermore, the TIS-NSFETs exhibit excellent immunity to overetched S/D recess depth variations. Additionally, the thermal characteristics of the TIS scheme are compared to that of the bottom oxide (BOX) scheme forming dielectrics beneath the S/D epitaxies, one of the methods used to suppress trpbt. Lattice temperature caused by self-heating and thermal resistance in the TIS-NSFETs are much lower than that in the BOX-NSFETs for both n/p-type devices. The thermal advantage of TIS-NSFETs compared to BOX-NSFETs is confirmed in both DC and AC conditions, similar to an actual operating environment. Therefore, the proposed TIS scheme is highly recommended to eliminate the undesired trpbt without critical DC/AC degradation and to resolve poor heat dissipation problems in the BOX scheme simultaneously.

We analyzed the performance, power, area of 3 nm node fin and nanosheet (NS) field-effect transistors (FETs) implementing buried power rail (BPR) after full calibration to 5 nm node hardware. Fin-shaped FETs (FinFETs) have smaller RC delay than do NS FETs (NSFETs) under the same footprint and two-fin configuration. Larger number of NS channels boost drive currents but also increase gate capacitances as a tradeoff. Compared with 7 and 3 nm standard cells achieve 75% cell area scaling in average. Cells using BPR decrease delay, transition time, internal power, and pin capacitances under the same area. Larger cells such as D-flip flop (DFF) and XOR decrease those further because the parasitic capacitances of metal layers between signal and power/ground decrease much. NS-based cells using BPR can improve delay and transition time by increasing the number of NS channels, but increase internal power and pin capacitance. Overall, fin-based cells using BPR have smaller energy delay product by 12% compared with those without BPR and by 10% compared with NS-based cells using BPR.

In this study, the self-heating effect (SHE) of sub-3-nm node forksheet (FS) field-effect transistors (FETs) and nanosheet (NS) FETs were systematically analyzed using a fully calibrated technology computer-aided design (TCAD) simulation. The electrothermal characteristics of FSFETs differ from those of NSFETs owing to a unique structural feature, namely, the SiN wall. The SiN wall of FSFETs reduces the gate metal, enhancing the electrical characteristics; however, the thermal characteristics deteriorate as the SiN wall inhibits heat dissipation. The evaluation of electrothermal properties using power–delay product and thermal resistance indicated that FSFETs were superior to NSFETs at the single device level; furthermore, in ring oscillators (RO), FSFETs are faster and have lower average power consumption and maximum lattice temperature than NSFETs. Owing to low maximum lattice temperature variations, FSFETs were less impacted by the SHE-induced hot carrier injection (HCI) and bias temperature instability (BTI) lifetime degradation at iso-frequency. This study, therefore, validates FSFETs targeting sub-3-nm nodes considering SHE and shows the superiority of FSFETs over NSFETs.

The inner spacer thickness (T_IS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T_IS variation (ΔT_IS). The gate length (L_G) depends on the T_IS. Thus, the DC/AC performance is significantly affected by ΔT_IS. Because the effects of ΔT_IS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔT_IS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (tr_pbt) should be considered with ΔT_IS because the gate controllability over tr_pbt is significantly dependent on ΔT_IS,B. If the S/D recess depth (T_SD) variation cannot be completely eliminated, reducing ΔT_IS,B is crucial for suppressing the effects of tr_pbt. It is noteworthy that reducing ΔT_IS,B is the most important factor when the T_SD variation occurs, whereas reducing ΔT_IS,T and ΔT_IS,M is crucial in the absence of T_SD variation to minimize the DC performance variation. As the T_IS increases, the gate capacitance (C_gg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of C_gg to each ΔT_IS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since T_SD of 5 nm increases the off-state current (I_off) sensitivity to ΔT_IS,B by a factor of 22.5 in NFETs, the ΔT_IS,B below 1 nm is essential for further scaling and yield enhancement.

The optimal inner spacer length ( $\textit{L}_{\text{IS}}$ ) for each layer in nanosheet (NS) field-effect transistors (FETs) was investigated using a technology computer-aided design (TCAD) simulation. Although gate-all-around (GAA) NS channels show excellent electrical characteristics, the parasitic channels formed in the punchthrough stopper (PTS) region show poor electrical characteristics. Further, the PTS region is susceptible to source/drain recess depth ( $\textit{T}_{\text{SD}}$ ) variations, which can cause considerable punchthrough current ( $\textit{I}_{\text{PT}}$ ). Hence, owing to the difference in the electrical properties of the NS channels and PTS region, the gate length ( $\textit{L}_{\text{g}}$ ) must be optimized for each channel. This study proposes a novel scheme that can selectively adjust the $\textit{L}_{\mathbf{g}}$ by stacking Si/SiGe layers with different germanium mole fractions. Consequently, shortening the $\textit{L}_{\text{IS}}$ at the bottom alone can considerably decrease the $\textit{I}_{\text{PT}}$ without a large increase in the gate capacitance ( $\textit{C}_{\text{gg}}$ ). In the NSFETs with $\textit{T}_{\text{SD}}$ $=$ 4 nm, the OFF-state current ( $\textit{I}_{\text{off}}$ ) decreased by 24.0%, while the $\textit{C}_{\text{gg}}$ increased by 5.2%. When comparing the performance of the NSFETs with the different $\textit{L}_{\text{IS}}$ combinations at the same $\textit{I}_{\text{off}}$ , the RC delay was improved by up to 19.5% ( $\textit{T}_{\text{SD}}$ $=$ 4 nm) and 5.3% ( $\textit{T}_{\text{SD}}$ $=$ 0 nm) compared to the NSFETs with a uniform $\textit{L}_{\text{IS}}$ . The proposed scheme is highly feasible as it does not require additional process steps. Additionally, since the gate controllability of each channel can be adjusted separately, the proposed scheme enables the performance optimization of the NSFETs.

This article presents a thorough investigation of the optimization of asymmetries in vertical-transport nanosheet field-effect transistors (VFETs), considering both asymmetric source/drain (S/D) structures and channel tapering. For asymmetric S/D configurations, n-type FETs (nFETs) exhibit smaller $\textit{RC}$ delay in the top-source (TopS) configuration, wherein the source has a shorter current path and less voltage drop. Conversely, p-type FETs (pFETs) exhibit smaller $\textit{RC}$ delay in the bottom-source (BotS) configuration owing to the dominant effect of asymmetric channel stress over the current path difference. Meanwhile, channel tapering significantly affects the optimization of asymmetric VFETs, especially for nFETs. Considering channel tapering, nFET with the smallest $\textit{RC}$ delay is the BotS configuration, in contrast to the untapered case, whereas BotS configuration is still the optimal structure for pFETs, regardless of the channel tapering. Finally, optimal structures of asymmetric VFETs are presented for various channel widths based on a comparison of the power–delay product (PDP). In nFETs, BotS configuration is optimal for wide channel widths; however, the TopS becomes superior as the channel width decreases in terms of PDP. Meanwhile, optimal structures for pFETs are BotS configurations regardless of the channel tapering and width. For various system-on-chip (SoC) applications, nFETs require a more detailed design than pFETs. Consequently, this study affords comprehensive insights for optimizing VFETs suitable for various applications.