Process (systematic) variations of sub-5-nm node fin field-effect transistors (FinFETs) and nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully calibrated TCAD. All the process parameters consisting of front-end- as well as middle-of-line structure were independently randomized within feasible process conditions. A novel process scheme called source/drain patterning (SDP), having a superior performance by decreasing outer fringing capacitance through the downsized source/drain (S/D) epi, has also been analyzed for the variability study. SDP FinFETs have smaller variations of threshold voltages (Vth), off-state currents (Ioff), and effective currents (Ieff) than conventional ones because the subfin leakage is effectively controlled by bottom oxide (BO) beneath the source/drain instead of high punchthrough-stopper doping. The Spearman's correlation results between process parameters, Ioff, and Ieff, showed that the process parameters affecting the short-channel effects vary Ioff and Ieff greatly. Especially, the most critical one was the fin width (Wfin) for FinFETs. SDP NSFETs have the smallest variations of Vth, Ioff, and Ieff. The BO blocks the bottom leakage completely, and the variations of nanosheet (NS) thickness (TNS) are much smaller than those of Wfin due to the different process flows: epitaxial growth for TNS versus patterning for Wfin. Therefore, NSFETs are promising to reduce the variations of Vth, Ioff, and Ieff in the sub-5-nm node.

We analyzed the performance, power, area of 3 nm node fin and nanosheet (NS) field-effect transistors (FETs) implementing buried power rail (BPR) after full calibration to 5 nm node hardware. Fin-shaped FETs (FinFETs) have smaller RC delay than do NS FETs (NSFETs) under the same footprint and two-fin configuration. Larger number of NS channels boost drive currents but also increase gate capacitances as a tradeoff. Compared with 7 and 3 nm standard cells achieve 75% cell area scaling in average. Cells using BPR decrease delay, transition time, internal power, and pin capacitances under the same area. Larger cells such as D-flip flop (DFF) and XOR decrease those further because the parasitic capacitances of metal layers between signal and power/ground decrease much. NS-based cells using BPR can improve delay and transition time by increasing the number of NS channels, but increase internal power and pin capacitance. Overall, fin-based cells using BPR have smaller energy delay product by 12% compared with those without BPR and by 10% compared with NS-based cells using BPR.

We analyze the electrical coupling effect of a fork-shaped field-effect transistor (FSFET) and compare FSFET and the nanosheet FET (NSFET) in terms of logic cell power, performance, and area. FSFET enables excellent scaling and is a promising candidate to replace NSFET at the sub 3-nm node. However, FSFETs are vulnerable to electrical coupling because n/p-type FETs (N/PFETs) are close to each other with the dielectric wall in the middle. This electrical coupling causes threshold voltage shift and increases in subthreshold slope, ON-current, and drain-induced barrier lowering (DIBL). Since the gate bias of the adjacent device has a greater effect than the source and drain, the coupling effect occurs more when the gates of N/PFETs are split. Our results show that small wall, small channel width, and high wall permittivity cause a significant electrical coupling in a sub 3-nm node. Coupling within the criteria can be secured for an FSFET with a 15-nm channel width by applying a 17-nm SiO $_{\text{2}}$ wall. With these coupling guidelines, the FSFET logic cell shows up to 21% improvement in an area compared to NSFET at the 15-nm channel width. Compared with NSFET, the FSFET shows an almost similar performance at the same power; in this case, the area improves by 15.5%–16.4%. Overall, FSFET should be designed to improve the electrical coupling, and FSFET can achieve almost the same power and performance as NSFET in a small area.

A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a large proportion of the device size irrespective of the active channel area. However, this problem was solved by patterning the low-k regions prior to S/D formation by preventing the lateral overgrowth of S/D epitaxy; the so-called S/D patterning (SDP). Its smaller S/D epitaxy decreased the average longitudinal channel stresses and drive currents for NFETs. However, the small diffusions of the boron dopants into the channel regions improved the short-channel effects and alleviated the drive current reduction for PFETs. Gate capacitances decreased greatly by reducing outer-fringing capacitances between the metal-gate stack and S/D regions. Through SPICE simulation based on the virtual source model, operation frequencies and dynamic powers of 15-stage ring oscillators were studied. SDP FinFETs have better circuit performances than the conventional and bottom oxide bulk FinFETs along with smaller active areas, promising for further area scaling through simple and reliable S/D process.

In this study, the self-heating effect (SHE) of sub-3-nm node forksheet (FS) field-effect transistors (FETs) and nanosheet (NS) FETs were systematically analyzed using a fully calibrated technology computer-aided design (TCAD) simulation. The electrothermal characteristics of FSFETs differ from those of NSFETs owing to a unique structural feature, namely, the SiN wall. The SiN wall of FSFETs reduces the gate metal, enhancing the electrical characteristics; however, the thermal characteristics deteriorate as the SiN wall inhibits heat dissipation. The evaluation of electrothermal properties using power–delay product and thermal resistance indicated that FSFETs were superior to NSFETs at the single device level; furthermore, in ring oscillators (RO), FSFETs are faster and have lower average power consumption and maximum lattice temperature than NSFETs. Owing to low maximum lattice temperature variations, FSFETs were less impacted by the SHE-induced hot carrier injection (HCI) and bias temperature instability (BTI) lifetime degradation at iso-frequency. This study, therefore, validates FSFETs targeting sub-3-nm nodes considering SHE and shows the superiority of FSFETs over NSFETs.

The inner spacer thickness (T_IS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T_IS variation (ΔT_IS). The gate length (L_G) depends on the T_IS. Thus, the DC/AC performance is significantly affected by ΔT_IS. Because the effects of ΔT_IS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔT_IS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (tr_pbt) should be considered with ΔT_IS because the gate controllability over tr_pbt is significantly dependent on ΔT_IS,B. If the S/D recess depth (T_SD) variation cannot be completely eliminated, reducing ΔT_IS,B is crucial for suppressing the effects of tr_pbt. It is noteworthy that reducing ΔT_IS,B is the most important factor when the T_SD variation occurs, whereas reducing ΔT_IS,T and ΔT_IS,M is crucial in the absence of T_SD variation to minimize the DC performance variation. As the T_IS increases, the gate capacitance (C_gg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of C_gg to each ΔT_IS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since T_SD of 5 nm increases the off-state current (I_off) sensitivity to ΔT_IS,B by a factor of 22.5 in NFETs, the ΔT_IS,B below 1 nm is essential for further scaling and yield enhancement.