This article presents a bidirectional long short-term memory (LSTM) model for the detection of landslides. Previous uses of machine learning (ML) in this setting have demonstrated its general potential, which necessitates the implementation of a suitable algorithm. Landslides are natural disasters that can cause significant destruction and disruption in the affected areas. Early detection is the key to minimizing the impact of landslides, so it is important to develop accurate and efficient models. An area selected for this study is located in Mawiongrim, Meghalaya, India, which is an active landslide zone. The proposed model uses a bidirectional LSTM to capture the temporal patterns of the input data collected from a long-term real-time monitoring system set up in the area. To evaluate the effectiveness of the predictions, the model is trained using a data set composed of various landslide-related characteristics, such as topography, rainfall, hydrological, and soil properties. The results show that the suggested model is capable of detecting landslides with greater accuracy and the lowest error value relative to other models. Additionally, the model is also able to provide a real-time warning system, making it a viable tool for early landslide detection. The research also highlights the prediction models for matric suction and groundwater level, which are crucial in determining slope stability.

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.

One of the efficient design methodologies for large scale system on a chip (SoC) is IP-based design. In this methodology, a system is considered as a set of components and interconnects among them. The designers try to reuse existing IPs as much as possible. Communications among components have to be conducted using a common protocol, however, IPs available today use various communication protocols. Thus the protocol conversion is one of the most important topics in IP-based design (Gajski et al., 2000). In this paper, we propose a method for automatic protocol transducer synthesis which is applicable to complex protocols. The main idea of our proposed method is division of the exploration space into smaller ones for avoiding explosion of the exploration space, namely with a divide and conquer approach. We demonstrate our method by synthesizing transducers which translate between the real and complicated protocols with advanced features such as non-blocking transactions and out-of-order transactions.

In this article, we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed “attribute statements” in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are also presented.

Multiplier circuit covers a more extensive area of embedded system application in digital signal processing, cryptography, and multimedia. Nonstandard implementations and custom optimization are being done to reduce the size of multipliers. The circuit became prone to a buggy, and hence the demand for verification increased. Formal verification methods, such as satisfiability (SAT), symbolic computer algebra (SCA), and binary decision diagrams (BDDs) have made massive progress over the last few decades. However, these methods are insufficient to verify the optimized multipliers. SAT-based equivalence checking is computationally expensive. SCA-based backward rewriting is limited to algebraic-friendly multipliers. The complexity of BDDs is exponential with the input size. Although, by allowing an additional variable method, the size of the BDD is limited to 4th degree polynomial of the number of the inputs, this method is not explored to verify optimized multipliers. This article focus on verifying integer multipliers with diverse architectures. We propose an algorithm for the direct construction of BDDs without traversing circuits and generate BDDs up to 1024 bits. We utilize the additional variable method and constructing BDDs using high-to-low variable ordering. We reduce the complexity of BDD size to a 3rd degree polynomial. We generate BDDs and verify the multipliers with various architectures up to 64 bits. We propose a method to verify optimized multipliers by checking equivalence and verifying up to 32-bits optimized multipliers. We do the error tolerance analysis of our approach by inserting bugs in a circuit at various locations.