In asynchronous circuit synthesis, the direct translation method, whereby circuits are derived from Petri net (PN) (1) specifications directly, has not evolved any automatic tools. This paper describes a design method based on direct translation techniques, incorpo- rating refinement, optimization and an automatic tool.

Neuromorphic systems are bio-inspired and have the potential to break through the bottleneck of existing intelligent systems. This paper proposes a neuromorphic high-speed object recognition method based on DVS and SpiNNaker and implements a system in which an OR logic aggregation algorithm is used to acquire sufficient effective information and the asynchronous sparse computing mechanism of SNNs is exploited to reduce the computation. The experiment’s results show that the object detection rate of the designed system is more than 99% at the rotating speed of 900~2300 rpm; its response time is within $2.5 \mathrm{ms}$; and it requires 96.3% less computation than traditional recognition systems using the same scaled ANN.

In this paper, two approximate Radix-4 Booth encoders AR4BE1 and AR4BE2 (Approximate Radix-4 Booth Encoder1, 2) are proposed to achieve great accuracy-cost trade-off, and a series of signed approximation multipliers (SAMs) are designed based on a hybrid coding approach, where the most significant bits (MSB) use exact radix-4 encoder, and the least significant bits (LSB) use the proposed AR4BE1 and AR4BE2. And a simple error compensation circuit is used to reduce the accuracy loss in partial product array reduction. The proposed SAMs can be reconfigured for different applications with different accuracy-cost trade-off requirement. We comprehensively evaluate the SAMs with respect to both hardware implementation and error analysis. Compared to the exact multiplier, the highest accuracy multiplier H10M6L0, has 22.8%, 32.1%, and 18.4% reduction in area, power consumption, and delay, respectively. The case study for image edge detection also proves the validity of the proposed SAMs in error-tolerant application.

A dynamic global security-aware synthesis flow using the SystemC language is presented. SystemC security models are first specified at the system or behavioural level using a library of SystemC behavioural descriptions which provide for the reuse and extension of security modules. At the core of the system is incorporated a global security-aware scheduling algorithm which allows for scheduling to a mixture of components of varying security level. The output from the scheduler is translated into annotated nets which are subsequently passed to allocation, optimisation and mapping tools for mapping into circuits. The synthesised circuits incorporate asynchronous secure power-balanced and fault-protected components. Results show that the approach offers robust implementations and efficient security/area trade-offs leading to significant improvements in turnover.

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b].

A range reduction method for shift-and-add algorithms for exponential functions is proposed in this paper. An exponential function accelerator with this method and radix-16 shift-and-add algorithm has been implemented in SMIC 55 nm CMOS process. Compared with the existing method, the proposed method reduces the latency (cycles) by 33% and 20% for 16 and 32-bit precision results, respectively; thereby increasing the throughput to 50M exp/s and reducing the power consumption to 4.6 pJ/exp. In addition, this method saves die area since no arithmetic units are adopted. This exponential accelerator is supposed to be used in a neuromorphic chip for spiking neural network modeling.