Networks‐on‐chip (NoC) is a communication paradigm that has emerged to tackle different on‐chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal‐based NoC pursuit offers limited scalability with the relentless technology scaling especially in global communications. To meet the scalability demand, this study proposes a new hybrid architecture empowered by both metal interconnect and Zenneck surface waves interconnects (SWIs). This architecture reduces the NoC average hop count between any communication pairs, which has been reflected as a better average delay and throughput. Furthermore, SWI enables more efficient power dissipation and faster cross the chip signal propagation. The authors’ initial results based on a cycle‐accurate simulator demonstrate the effectiveness of the proposed system architecture, such as significant power reduction (23%), large average delay reduction (34%) and higher throughput (35%) compared with regular NoC. These results are achieved with negligible hardware and area overhead. This study explores promising potentials of SWI for future complex global communication.

For over 50 years, Amdahl's Law has been the hallmark model for reasoning about performance bounds for homogeneous parallel computing resources. As heterogeneous, many‐core parallel resources continue to permeate into the modern server and embedded domains, there has been growing interest in promulgating realistic extensions and assumptions in keeping with newer use cases. This study aims to provide a comprehensive review of the purviews and insights provided by the extensive body of work related to Amdahl's law to date, focusing on computation speedup. The authors show that a significant portion of these studies has looked into analysing the scalability of the model considering both workload and system heterogeneity in real‐world applications. The focus has been to improve the definition and semantic power of the two key parameters in the original model: the parallel fraction ( f ) and the computation capability improvement index ( n ). More recently, researchers have shown normal‐form and multi‐fraction extensions that can account for wider ranges of heterogeneity, validated on many‐core systems running realistic workloads. Speedup models from Amdahl's law onwards have seen a wide range of uses, such as the optimisation of system execution, and these uses are even more important with the advent of the heterogeneous many‐core era.

Traditional speedup models, such as Amdahl's law, Gustafson's, and Sun and Ni's, have helped the research community and industry better understand system performance capabilities and application parallelizability. As they mostly target homogeneous hardware platforms or limited forms of processor heterogeneity, these models do not cover newly emerging multi-core heterogeneous architectures. This paper reports on novel speedup and energy consumption models based on a more general representation of heterogeneity, referred to as the normal form heterogeneity, that supports a wide range of heterogeneous many-core architectures. The modelling method aims to predict system power efficiency and performance ranges, and facilitates research and development at the hardware and system software levels. The models were validated through extensive experimentation on the off-the-shelf big.LITTLE heterogeneous platform and a dual-GPU laptop, with an average error of 1% for speedup and of less than 6.5% for power dissipation. A quantitative efficiency analysis targeting the system load balancer on the Odroid XU3 platform was used to demonstrate the practical use of the method.

This article studies the interplay between the performance, energy, and reliability (PER) of parallel-computing systems. It describes methods supporting the meaningful cross-platform analysis of this interplay. These methods lead to the PER software tool, which helps designers analyze, compare, and explore these properties. The web extra at https://youtu.be/aijVMM3Klfc illustrates the PER (performance, energy, and reliability) tool, expanding on the main engineering principles described in the article.

In asynchronous circuit synthesis, the direct translation method, whereby circuits are derived from Petri net (PN) (1) specifications directly, has not evolved any automatic tools. This paper describes a design method based on direct translation techniques, incorpo- rating refinement, optimization and an automatic tool.

Power supply integrity has become a critical concern with the rapid shrinking feature size and the ever increasing power consumption in nanometre scale integration. In particular, on-chip communication in platforms such as networks-on-chip (NoC) dictates the power dissipation and overall system performance in multicore systems and embedded computing architectures. These architectures require a dedicated tool for analyzing the power supply noise which must embed distinctive communication characteristics and spatial parameters. In this paper, we present a tool dedicated to determining the on-chip V_DD drops due to communication workload in NoCs. This tool integrates a fast power grid model, an NoC simulator, an on-chip link model, and a microarchitectural power model for router. The model has been rigorously verified using SPICE simulations. The proposed model and tools are further exemplified through analyzing the impact of power supply noise for NoC links. Statistical timing analysis of NoC links in the presence of power supply noise was performed to evaluate the bit error rates (BERs). This work would enable better understanding of the tradeoffs existing in the design of NoCs, and the induced power supply noise due to on-chip communication. This understanding is crucial for the analysis of the quality of service (QoS) of communication fabrics in NoCs at the early design stages.