Currently, designing low-power complex embedded systems is a main challenge for corporations in a large number of electronic domains. There are multiple motivations which lead designers to consider low-power design such as increasing lifetime, improving battery longevity, limited battery capacity, and temperature constraints. Unfortunately, there is a lack of efficient methodology and accurate tool to obtain power/energy estimation of a complete system at different abstraction levels. This paper presents a global framework for power/energy estimation and optimization of heterogeneous multiprocessor system-on-chip (MPSoC). Within this framework, a power modeling methodology is defined, and an open platform is developed. Our methodology takes into account all the embedded system relevant aspects; the software, the hardware, and the operating system. The platform stands for Open Power and Energy Optimization PLatform and Estimator (Open-PEOPLE). It includes diverse estimation tools with respect to their abstraction levels in order to cover the overall design flow. Starting from functional estimation and down to real boards measurements, our platform helps designers to develop new power models, to explore new architectures, and to apply optimization techniques in order to reduce energy and power consumption of the system. The usefulness and the effectiveness of the proposed power estimation framework is demonstrated through a typical embedded system conceived around the Xilinx Virtex II Pro FPGA platform.

This paper deals with real-time scheduling of homogeneous multicore platforms powered by a battery to be periodically recharged. A system is composed of reconfigurable real-time dependent and periodic tasks to be assigned to different cores interconnected by a network-on-chip (NoC). The system is subject to reconfigurations, which are automatic operations allowing the addition and/or removal of tasks as well as their exchanged messages on the NoC. Consequently, any reconfiguration can violate real-time and energy constraints on cores as well as the NoC when the energy is unavailable until the next recharge. A novel periodic task model based on elastic coefficients and a new scheduling strategy are proposed to compute useful temporal parameters allowing for tasks and messages to meet the related constraints while controlling the communication cost on the NoC. This strategy is compared with an integer linear programming-based optimal solution, and a tool named OptimalMappingTasks is developed to run different simulations that prove the originality of this paper's contribution.

Configuration prefetching is known as an effective technique for hiding the reconfiguration delay of hardware accelerators in Partial Region FPGA. In prefetching, a hardware task can be loaded as soon as possible even if it cannot execute immediately after its reconfiguration due to the involvement of dependencies with other tasks. But due to the access in advance, the configuration delay is hidden. This method can be compared with a software prefetching in the processor domain. However, in the context of reconfigurable architecture, the difficulties come from the dependencies of prefetching with task scheduling and placement aspect. In this paper, we introduce an run-time spatio-temporal scheduling heuristic for dependent tasks executed on 2D heterogeneous FPGA. The objective is to reduce the reconfiguration delay of tasks, thus minimize the total execution time of an application. To achieve it, our proposed heuristic tries to prefetch tasks as early as possible while considering two factors: the priority of new tasks to be loaded and the placement decision to avoid conflicts among tasks. The experiments show that our heuristic reduces significantly the overall execution time by 22% compared to a non-prefetching method and approximately 5% compared to other prefetching methods.

Since several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in System-on-Chip (SoC). Especially, faults occurring to Network-on-Chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among Intellectual Properties (IPs). Furthermore, existing fault tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the Bit Shuffling meThod (BiSuT) for fault tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at run-time, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on Least Significant Bits (LSBs), instead of keeping them on Most Significant Bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to existing approaches, like Hamming code.

Current embedded systems are increasingly used to support high-performance applications. This is due to the diffusion of these systems in the domain of mobile devices and the need of a large number of services required from these systems. To support the execution of these applications, several architectures based on CPU, GPU or FPGA have been developed and are still under investigation. When the application demands both performance and flexibility, architectures based on several types of execution resources are of high benefit. In this context, designers define architectures which include all the necessary resources on the same chip, also called “Multiprocessor System on a Chip” (MPSoC). Image processing is one of the major applications in embedded domain, which requires high effort in computation. Image processing for medicine, automotive, and for video compression is the main algorithm that has been addressed by the authors of the Design and Architecture for Image and Signal Processin ...