The high degree of miniaturization in the electronics industry has been, for several years, a driver to push embedded systems to different fields and applications. One example is safety-critical systems, where the compactness in the form factor helps to reduce the costs and allows for the implementation of new techniques. The automotive industry is a great example of a safety-critical area with a great rise in the adoption of microelectronics. With it came the creation of the ISO 26262 standard with the goal of guaranteeing a high level of dependability in the designs. Other areas in the safety-critical applications domain have similar standards. However, these standards are mostly guidelines to make sure that designs reach the desired dependability level without explicit instructions. In the end, the success of the design to fulfill the standard is the result of a thorough verification process. Naturally, the goal of any verification team dealing with such important designs is complete coverage as well as standards conformity, but as these are complex hardware, complete functional verification is a difficult task. From the several techniques that exist to verify hardware, where each has its pros and cons, we studied six well-established in academia and in industry. We can divide them into two categories: simulation, which needs extremely large amounts of time, and formal verification, which needs unrealistic amounts of resources. Therefore, we conclude that a hybrid approach offers the best balance between simulation (time) and formal verification (resources).

This paper presents the results from research work done in the field of reconfigurable architectures and systems. Dynamic and partial reconfiguration has mainly been investigated as a way to configure functionalities in hardware on-demand, controlled either by the user or by the system itself. This paper presents work that was aimed at applying hardware reconfiguration even for run-time adaptation of functional implementation in order to enable self-optimization of power and performance according to the run-time specific requirements of the application.

Configuration prefetching is known as an effective technique for hiding the reconfiguration delay of hardware accelerators in Partial Region FPGA. In prefetching, a hardware task can be loaded as soon as possible even if it cannot execute immediately after its reconfiguration due to the involvement of dependencies with other tasks. But due to the access in advance, the configuration delay is hidden. This method can be compared with a software prefetching in the processor domain. However, in the context of reconfigurable architecture, the difficulties come from the dependencies of prefetching with task scheduling and placement aspect. In this paper, we introduce an run-time spatio-temporal scheduling heuristic for dependent tasks executed on 2D heterogeneous FPGA. The objective is to reduce the reconfiguration delay of tasks, thus minimize the total execution time of an application. To achieve it, our proposed heuristic tries to prefetch tasks as early as possible while considering two factors: the priority of new tasks to be loaded and the placement decision to avoid conflicts among tasks. The experiments show that our heuristic reduces significantly the overall execution time by 22% compared to a non-prefetching method and approximately 5% compared to other prefetching methods.

Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reconfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reconfiguration due to the lack of an internal configuration port. However, a virtual internal configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for internal configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reconfiguration over JCAP.

This paper describes the RTL-to-layout implementation of the PACT XPP-III coarse-grained reconfigurable architecture (CGRA). The implementation activity was strictly based on a hierarchical approach in order to exploit performance optimization at all levels, as well as guarantee maximum scalability and provide a portfolio of IP-blocks that could be reused to build different configurations and embodiments of the same CGRA template. The final result can be seamlessly introduced in any SoC design flow as embedded accelerator. It is designed in STMicroelectronics 90nm GP technology, occupies 42.5 mm², delivers 13 16-bit GOPS (0.8 GOPS/mW, 10 MOPS/mW) and has a measured max frequency of 150 MHZ, requiring a measured 13 mW/MHz dynamic power, 93 mW static. A silicon prototype was also produced embedding XPP-III in a complex system-on-chip including an ARM processor as system controller as well as different ASIC blocks.