Recent technological advancements have led to a significant increase in electroencephalogram (EEG)-based applications, ranging from clinical diagnosis and brain computer interfaces (BCI) to sleep studies and the monitoring of cognitive tasks. However, raw EEG signals are highly susceptible to artifacts, which hinder accurate analysis and interpretation of brain signals. Traditional artifact removal techniques often fall short owing to their linear assumptions and limited generalizability. Deep learning (DL) based approaches have shown remarkable potential for capturing nonlinear and complex features of EEG signals. This review provides a comprehensive overview of state-of-the-art deep learning models developed for EEG denoising, highlighting their architectural designs, strengths, limitations, and performance analysis. In addition, the study emphasizes the importance of accurate evaluation frameworks and benchmarking, as well as the challenges of generalizability and interpretability. Future research directions include the integration of hybrid architectures, self-supervised learning, and real-time implementation. This article serves as a resource for researchers aiming to advance EEG denoising through modern deep learning approaches.

Cancer is a disease of uncontrolled cell growth, beginning with one cell or a small group of cells, spreading over to different organs, and ultimately causing death if not controlled. According to GLOBOCAN fact sheet 2012, cancer-related mortality accounts for 8.2 million worldwide, out of which breast cancer alone accounts for 0.52 million.¹ Breast cancer begins as a premalignant disease and reaches to its advanced and/or metastatic stage through various phases of tumor progression. The nonmodifiable factors responsible for breast cancer are the female gender itself, age, BRCA1 and BRCA2 genes, and personal factors such as a long menstrual history, use of oral contraceptives, and having first child after age 30 or nulliparous.² Among the modifiable factors, the major risks are being overweight, lifestyle, taking hormone replacement therapy, taking birth control pills, drinking alcohol, having tobacco, etc. Once a breast tumor is developed, its growth and progression are always supported by the surrounding tumor microenvironment. It is supposed to be composed of a variety of cell types including endothelial cells, pericytes, smooth-muscle cells, fibroblasts of various phenotypes, myofibroblasts, immune cells, natural killer lymphocytes, and antigen-presenting cells, such as macrophages and also dendritic cells. They are often characterized by conditions like hypoxia, nutrient deprivation, acidosis, abnormal tumor angiogenesis, aberrant stroma, etc.^3,4 There are several proteins secreted during the progression of the disease. These proteins play a key role in the biological pathway leading to the development and prognosis of the disease. The identification and characterization of these proteins (biomarkers) may lead to a better understanding of the disease patterns. However, the heterogeneous nature of breast cancer makes biomarker identification a challenging task and alternative strategies are needed to address this problem by detecting the cancer early.

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.

The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs.