In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel-surround gate-oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs.

In this paper, a gate-all-around (GAA) charge plasma-based dopingless dual material gate nanowire FET is proposed (CP-DM). This structure is further explored by adding gate-stack (high-k + SiO2) feature (CP-GS-DM). In these dopingless structures, source/drain is induced using a charge plasma concept by an appropriate selection of work functions for source/drain electrodes. The dopingless devices offer low thermal budget with easier fabrication steps and reduced random dopant fluctuations effect. Both the dopingless structures are investigated for analog performance, and results are compared with those obtained from the GAA junctionless dual material (JL-DM) gate and the JL gate-stacked DM gate (JL-GS-DM), respectively. The charge plasma-based dopingless devices when compared with their JL counterpart show improvement in drive current (I _D ), transconductance (g _m ), transconductance gain factor (g _m /I _D ), output conductance (g _ds ), early voltage (V _AE ), intrinsic gain (A _v ), drain-induced barrier lowering, and subthreshold slope. Thus, dopingless structures show enhanced analog performance with reduced short channel effects. The charge plasma based dopingless gate stacked dual material gate (CP-GS-DM) shows the best performance of all the structures. The analysis is further carried out for investigating the device design parameters effect on performance, namely, total gate length, L _G , and ratio of control gate length to total gate length, L _M1 /L _G . This way dopingless charge plasma-based devices incorporate DM and GS features that make these devices interesting and reliable candidatesfor analog applicationwith cost-effective fabrication.

A novel device architecture charge plasma-based Ring-TFET (CP-RingTFET) has been described in this work. The ring structure of the proposed device uses a core-shell architecture with a drain at the center covered with the channel and followed by the source. The ring structure has the advantage of ultrascaling and mechanical strength as compared to the nanowire structure. The performance characteristics of the Ring-TFET are much better as compared to nanowire-TFET with similar physical dimensions. To investigate the impact of charge plasma on RingTFET architecture, various analog and linearity parameters have been studied; such as off-state current (Ioff), on-state current (Ion), Ion/Ioff, subthreshold slope (SS), gate-to-gate capacitance, transconductance (gm), transconductance gain factor (TGF), threshold voltage (VTH), higher-order transconductances, higher-order harmonic distortions, third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and higher-order voltage intercept points. The ability of the CP-RingTFET to enhance the performance of the proposed device is confirmed with the reduction of Ioff, improving Ion/Ioff, lower SS including the benefits of threshold voltage reduction.

In this paper, we have proposed dopingless gate all around (GAA) nanowire tunnel field-effect transistor (NWTFET) made up of dual-material channel (DMaC). Charge-plasma (CP) technique is used to induce the doping concentration of charge carriers in the intrinsic semiconductor. GAA structure uses zirconium silicate (IV) (ZrSiO₄)/silicon dioxide (SiO₂) for heterogeneous gate (HG) structure metalized with two different gate metals. Auxiliary gate (GM1) and tunneling gate (GM2) have different work functions, i.e., φ ₁ and φ ₂. The device physics is analyzed using electric field, charge carrier concentration, energy-band diagram, and tunneling rate across the structure. The effect of variation in φ ₁ and φ ₂ helps in the analysis of the ambipolar and analog behavior of the proposed device CP-dual metal-HG-DMaC-NWTFET. The reported ON-state current is 5.54 μA/μm, and the OFF-state current is approximately 0.1 aA/μm. The proposed device showed negligible ambipolar current (10⁻¹⁹ A/μm) as negative bias increases to VGS =-0.8 V making the device compatible for low-voltage applications.