High-performance temperature sensing is a key technique in modern Internet of Things. However, it is hard to attain a high precision while achieving a compact size for wireless sensing. Recently, metamaterials have been proposed to design a microwave, wireless temperature sensor, but precision is still an unsolved problem. By combining the high-quality factor (Q-factor) feature of a EIT-like metamaterial unit and the large temperature-sensing sensitivity performance of liquid metals, this paper designs and experimentally investigates an Hg-EIT-like metamaterial unit block for high figure-of-merit (FOM) temperature-sensing applications. A measured FOM of about 0.68 is realized, which is larger than most of the reported metamaterial-inspired temperature sensors.

The portable real-time electrocardiogram (ECG) is a convenient and promising electronic device for cardiovascular diseases patients. However, unlike wet gel electrodes in traditional clinical applications, dry electrodes are competent for comfortable long-time wearing and can prevent skin ulceration. Its ultra-high source impedance and electrode offset (EOS) make traditional chopper amplifiers with low input impedance and limited EOS range difficult to apply to this area. To overcome these challenges, this paper proposes a novel chopper amplifier topology. This architecture includes a gain control loop, a ripple reduction loop, and a DC-servo loop (DSL). The proposed sampling input stage and digital-analog hybrid DSL are employed to boost input impedance and extend the EOS handing range. Designed with a 0.18 µm 1P6M 1.8 V CMOS salicide process, the proposed chopper capacitively coupled instrumentation amplifier achieves an ultra-high input impedance of 120 GΩ (<0.05 Hz) or 2.1 GΩ (0.6~250 Hz), an EOS handing range of ±325 mV and a low noise of 1.9 μVrms at 0.6~250 Hz. It occupies an area of 0.36 mm² and only consumes a quiescent current of 11 μA.

This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications.

A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occupies 1.3% of the whole PLL area.