This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.

A high-speed and low-power driver employing a single bootstrap capacitor is reported. It outperforms the other CMOS bootstrap drivers in terms of power dissipation, performance, and active area, under the similar loading conditions and circuit parameters, when implemented in the triple-well 0.13-mum CMOS process from UMC

This paper presents a comprehensive overview and analysis of the state-of-the-art (SoA) in semi-passive or Battery-Assisted (BAP) Ultra-High Frequency (UHF) Radio Frequency Identification (RFID) sensor tags compliant with EPC Global G2/ISO-18000C. These tags operate on the same communication principle as fully passive sensor tags but incorporate a battery or an energy harvesting module. This additional power source extends communication ranges and enables power demanding applications using low power microcontrollers (MCUs) and higher-end sensors. This article also analyzes various key features, including tag integrated circuit (IC) architecture, types of energy harvesting modules, and communication range. The main conclusions are threefold. Firstly, selecting the appropriate tag IC requires a careful analysis its features such as sensitivity, sensor interfaces or data logging capabilities. For instance, among the solutions examined in the SoA, half of them opted for a tag IC capable of MCU communication via SPI or I2C buses. Secondly, it is essential to assess both the forward and backward communication links to leverage the sensitivity of the tag IC in BAP mode. Interestingly, only one third of the solutions in the SoA achieved the theoretical communication range anticipated by the tag IC sensitivity. Finally, an energy budget analysis is required to ensure that the energy generation suffices to meet the energy requirements of the tag. While most solutions rely on batteries as the energy source and analyze battery lifespan, only a few studies employing energy harvesters conduct an energy budget analysis due to the additional complexity involved.

A blood pressure sensor suitable for wireless biomedical applications is designed and optimized. State-of-the-art blood pressure sensors based on piezoresistive transducers in a full Wheatstone bridge configuration use low ohmic values because of relatively high sensitivity and low noise approach resulting in high power consumption. In this paper, the piezoresistance values are increased in order to reduce by one order of magnitude the power consumption in comparison with literature approaches. The microelectromechanical system (MEMS) pressure sensor, the mixed signal circuits signal conditioning circuitry, and the successive approximation register (SAR) analog-to-digital converter (ADC) are designed, optimized, and integrated in the same substrate using a commercial 1 μm CMOS technology. As result of the optimization, we obtained a digital sensor with high sensitivity, low noise (0.002 μV/Hz), and low power consumption (358 μW). Finally, the piezoresistance noise does not affect the pressure sensor application since its value is lower than half least significant bit (LSB) of the ADC.

In this paper, we present the design of a practical underwater sensor network for offshore fish farm cages. An overview of the current structure of an offshore fish farm, applied sensor network solutions, and their weaknesses are given. A mixed wireless–wired approach is proposed to mitigate the problem of wire breakage in underwater wired sensor networks. The approach is based on the serial arrangement of identical sections with wired and wireless interconnections areas. Wireless section alleviates underwater maintenance operations when cages are damaged. The analytical model of the proposed solution is studied in terms of maximum power transfer efficiency and the general formulas of the current in their transmitting antennas and sensor nodes are provided. Subsequently, based on simulations, the effects of parasitic resistance across the network are evaluated. A practical underwater sensor network to reach the 30 m depth with sensor nodes distanced 6 m is used to determine the proposal compliance with the ISO 11784/11785 HDX standard in its normal operation. Taking into account the cable breakage scenario, the results from experiments demonstrate the robustness of the proposed approach to keep running the sensor nodes that are located before the short circuit. Sensor node run time is reduced only 4.07% at most using standard values when a cable breakage occurs at the second deepest section.