We compare basic physical parameters of Al/sub 0.2/Ga/sub 0.8/N-GaN quantum well with In/sub 0.17/Al/sub 0.83/N/GaN and In/sub 0.17/Al/sub 0.83/N/In/sub 0.10/Ga/sub 0.90/N quantum well parameters, respectively. It is shown that in comparison to conventional AlGaN/GaN approach, structures based on InAlN/(In)GaN should exhibit two to three times higher quantum well polarization-induced charge. We use high electron mobility transistors (HEMT) analytical model to calculate InAlN(In)GaN HEMTs drain currents and transconductances. A 3.3 A/mm and 2.2 A/mm drain current was calculated for In/sub 0.17/Al/sub 0.83/N/In/sub 0.10/Ga/sub 0.90/N and In/sub 0.17/Al/sub 0.83/N/GaN HEMTs, respectively. This represents up to 205% current increase if compared with AlGaN/GaN HEMT and a record power performance can be expected for new structures.

Gate reliability of normally-off p-type-GaN/AlGaN/GaN high-electron mobility transistors grown on Si substrate subjected to forward bias stress at different gate voltages and temperatures was analyzed. Stress-induced gate current degradation was found to be consistent with the percolation process. Obtained time-to-breakdown data were interpreted using the Weibull statistics, and the maximum allowed gate operating voltage was estimated. The gate degradation was found to be weakly dependent on temperature with an activation energy of 0.1 eV.

An analytical model for threshold voltage calculation for metal-oxide-semiconductor GaN based high electron mobility transistors is proposed. This model includes polarization induced charges at each heterostructure interface/surface, surface donors, oxide/barrier interface traps charge, and interfacial and bulk fixed oxide charge. Applicability of the model is demonstrated on GaN/AlGaN/GaN MOS heterostructure capacitors with Al₂O₃ and HfO₂ gate dielectrics grown by atomic layer deposition with different barrier surface treatment and Al₂O₃ thicknesse.

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.

We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with source and drain contacts grounded). Degradation is analyzed by measuring the drain current, a threshold voltage, a Schottky contact barrier height, a gate leakage and an ideality factor, an access, and an intrinsic channel resistance, respectively. For the drain-gate bias <38 V parameters are only reversibly degraded due to charging of the pre-existing surface states. This is in a clear contrast to reported AlGaN/GaN HEMTs where an irreversible damage and a lattice relaxation have been found for similar conditions. For drain-gate biases over 38 V InAlN/GaN HEMTs show again only temporal changes for the negative gate bias stresses; however, irreversible damage was found for the off-state and for the semi-on stresses. Most severe changes, an increase in the intrinsic channel resistance by one order of magnitude and a decrease in the drain current by ∼70%, are found after the off-state ∼50 V drain-gate bias stresses. We conclude that in the off-state condition hot electrons may create defects or ionize deep states in the GaN buffer or at the InAlN/GaN interface. If an InAlN/GaN HEMT channel is opened during the stress, lack of the strain in the barrier layer is beneficial for enhancing the device stability.