Gate reliability of normally-off p-type-GaN/AlGaN/GaN high-electron mobility transistors grown on Si substrate subjected to forward bias stress at different gate voltages and temperatures was analyzed. Stress-induced gate current degradation was found to be consistent with the percolation process. Obtained time-to-breakdown data were interpreted using the Weibull statistics, and the maximum allowed gate operating voltage was estimated. The gate degradation was found to be weakly dependent on temperature with an activation energy of 0.1 eV.

An analytical model for threshold voltage calculation for metal-oxide-semiconductor GaN based high electron mobility transistors is proposed. This model includes polarization induced charges at each heterostructure interface/surface, surface donors, oxide/barrier interface traps charge, and interfacial and bulk fixed oxide charge. Applicability of the model is demonstrated on GaN/AlGaN/GaN MOS heterostructure capacitors with Al₂O₃ and HfO₂ gate dielectrics grown by atomic layer deposition with different barrier surface treatment and Al₂O₃ thicknesse.

A new methodology is developed to determine spatial location and properties of traps generated by electrical stressing of AlGaN/GaN high-electron mobility transistors, based on integrated optical and electrical analysis. Mild off-state stress increases irreversibly the number of traps located in the near-surface AlGaN region at the gate edge. A deep level with 0.45-eV activation energy in fresh devices changes its nature to interacting defect after the off-state stress, accompanied by an activation energy change. These results are consistent with trap generation in the near-surface AlGaN region at the gate edge related to high electric field and gate leakage current, as stressing does not result in the generation of cracks in the AlGaN layer.

Early stage degradation of AlGaN/GaN high electron mobility transistors (HEMTs) with different threading dislocation densities (TDDs) submitted to off-state voltage bias stress was studied. It was found that, for the stress conditions used, HEMTs with TDD ∼10¹⁰cm⁻² show pronounced degradation in terms of maximum drain current, gate-lag, and trap generation measured by drain current trapping characteristics, a slight degradation in gate leakage was observed also for HEMTs with TDD of ∼10⁸cm⁻², and no significant degradation for devices with TDD in the ∼10⁷cm⁻² range. The results illustrate the importance of TDD for degradation and reliability of AlGaN/GaN HEMTs.

The authors investigate $2\mu \mathrm{m}$ gate-length $\mathrm{In}\mathrm{Al}\mathrm{N}∕\mathrm{Ga}\mathrm{N}$ metal-oxide-semiconductor high-electron-mobility transistors (MOS HEMTs) with $12\mathrm{nm}$ thick ${\mathrm{Al}}_2{\mathrm{O}}_3$ gate insulation. Compared to the Schottky barrier (SB) HEMT with similar design, the MOS HEMT exhibits a gate leakage reduction by six to ten orders of magnitude. A maximal drain current density $(I_{\mathit{DS}}=0.9\mathrm{A}∕\mathrm{mm})$ and an extrinsic transconductance $(g_{me}=115\mathrm{mS}∕\mathrm{mm})$ of the MOS HEMT also show improvements despite the threshold voltage shift. An analytical modeling shows that a higher mobility of electrons in the channel of the MOS HEMT and consequently a higher number of electrons attaining the velocity saturation may explain the observed increase in $g_{me}$ after the gate insulation.