Hyperspectral imaging has emerged as an effective powerful tool in plentiful military, environmental, and civil applications over the last three decades. The modern remote sensing approaches are adequate for covering huge earth surfaces with phenomenal temporal, spectral, and spatial resolutions. These features make HSI more effective in various applications of remote sensing depending upon the physical estimation of identical material identification and manifold composite surfaces having accomplished spectral resolutions. Recently, HSI has attained immense significance in the research on safety and quality assessment of food, medical analysis, and agriculture applications. This review focuses on HSI fundamentals and its applications like safety and quality assessment of food, medical analysis, agriculture, water resources, plant stress identification, weed & crop discrimination, and flood management. Various investigators have promising solutions for automatic systems depending upon HSI. Future research may use this review as a baseline and future advancement analysis.

The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

Higher charge mobility, gate control, and better electrostatics are the key reasons that make carbon nanotube field effect transistor (CNTFET) a better candidate to become the successor of conventional CMOS transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21×compared to conventional 6T SRAM at 0.3V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02×and 1.85×, respectively. Moreover, the read/ write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.